Imported Upstream version 1.0 upstream/1.0
authorDevon Kearns <dookie@kali.org>
Fri, 10 Jan 2014 19:47:22 +0000 (12:47 -0700)
committerDevon Kearns <dookie@kali.org>
Fri, 10 Jan 2014 19:47:22 +0000 (12:47 -0700)
134 files changed:
.gitignore [new file with mode: 0644]
COMPILE [new file with mode: 0644]
CONFIG [new file with mode: 0644]
CREDITS.TXT [new file with mode: 0644]
HACK [new file with mode: 0644]
LEB128.h [new file with mode: 0644]
LICENSE.TXT [new file with mode: 0644]
LICENSE_LLVM.TXT [new file with mode: 0644]
MCDisassembler.h [new file with mode: 0644]
MCFixedLenDisassembler.h [new file with mode: 0644]
MCInst.c [new file with mode: 0644]
MCInst.h [new file with mode: 0644]
MCInstrDesc.c [new file with mode: 0644]
MCInstrDesc.h [new file with mode: 0644]
MCRegisterInfo.c [new file with mode: 0644]
MCRegisterInfo.h [new file with mode: 0644]
Makefile [new file with mode: 0644]
MathExtras.h [new file with mode: 0644]
README [new file with mode: 0644]
SStream.c [new file with mode: 0644]
SStream.h [new file with mode: 0644]
SubtargetFeature.h [new file with mode: 0644]
TODO [new file with mode: 0644]
arch/AArch64/AArch64BaseInfo.c [new file with mode: 0644]
arch/AArch64/AArch64BaseInfo.h [new file with mode: 0644]
arch/AArch64/AArch64Disassembler.c [new file with mode: 0644]
arch/AArch64/AArch64Disassembler.h [new file with mode: 0644]
arch/AArch64/AArch64GenAsmWriter.inc [new file with mode: 0644]
arch/AArch64/AArch64GenDisassemblerTables.inc [new file with mode: 0644]
arch/AArch64/AArch64GenInstrInfo.inc [new file with mode: 0644]
arch/AArch64/AArch64GenRegisterInfo.inc [new file with mode: 0644]
arch/AArch64/AArch64GenSubtargetInfo.inc [new file with mode: 0644]
arch/AArch64/AArch64InstPrinter.c [new file with mode: 0644]
arch/AArch64/AArch64InstPrinter.h [new file with mode: 0644]
arch/AArch64/mapping.c [new file with mode: 0644]
arch/AArch64/mapping.h [new file with mode: 0644]
arch/ARM/ARMAddressingModes.h [new file with mode: 0644]
arch/ARM/ARMBaseInfo.h [new file with mode: 0644]
arch/ARM/ARMDisassembler.c [new file with mode: 0644]
arch/ARM/ARMDisassembler.h [new file with mode: 0644]
arch/ARM/ARMGenAsmWriter.inc [new file with mode: 0644]
arch/ARM/ARMGenDisassemblerTables.inc [new file with mode: 0644]
arch/ARM/ARMGenInstrInfo.inc [new file with mode: 0644]
arch/ARM/ARMGenRegisterInfo.inc [new file with mode: 0644]
arch/ARM/ARMGenSubtargetInfo.inc [new file with mode: 0644]
arch/ARM/ARMInstPrinter.c [new file with mode: 0644]
arch/ARM/ARMInstPrinter.h [new file with mode: 0644]
arch/ARM/mapping.c [new file with mode: 0644]
arch/ARM/mapping.h [new file with mode: 0644]
arch/Mips/MipsDisassembler.c [new file with mode: 0644]
arch/Mips/MipsDisassembler.h [new file with mode: 0644]
arch/Mips/MipsGenAsmWriter.inc [new file with mode: 0644]
arch/Mips/MipsGenDisassemblerTables.inc [new file with mode: 0644]
arch/Mips/MipsGenInstrInfo.inc [new file with mode: 0644]
arch/Mips/MipsGenRegisterInfo.inc [new file with mode: 0644]
arch/Mips/MipsGenSubtargetInfo.inc [new file with mode: 0644]
arch/Mips/MipsInstPrinter.c [new file with mode: 0644]
arch/Mips/MipsInstPrinter.h [new file with mode: 0644]
arch/Mips/mapping.c [new file with mode: 0644]
arch/Mips/mapping.h [new file with mode: 0644]
arch/X86/X86ATTInstPrinter.c [new file with mode: 0644]
arch/X86/X86Disassembler.c [new file with mode: 0644]
arch/X86/X86Disassembler.h [new file with mode: 0644]
arch/X86/X86DisassemblerDecoder.c [new file with mode: 0644]
arch/X86/X86DisassemblerDecoder.h [new file with mode: 0644]
arch/X86/X86DisassemblerDecoderCommon.h [new file with mode: 0644]
arch/X86/X86GenAsmWriter.inc [new file with mode: 0644]
arch/X86/X86GenAsmWriter1.inc [new file with mode: 0644]
arch/X86/X86GenDisassemblerTables.inc [new file with mode: 0644]
arch/X86/X86GenInstrInfo.inc [new file with mode: 0644]
arch/X86/X86GenRegisterInfo.inc [new file with mode: 0644]
arch/X86/X86InstPrinter.h [new file with mode: 0644]
arch/X86/X86IntelInstPrinter.c [new file with mode: 0644]
arch/X86/mapping.c [new file with mode: 0644]
arch/X86/mapping.h [new file with mode: 0644]
bindings/Makefile [new file with mode: 0644]
bindings/const_generator.py [new file with mode: 0644]
bindings/java/.gitignore [new file with mode: 0644]
bindings/java/Makefile [new file with mode: 0644]
bindings/java/README [new file with mode: 0644]
bindings/java/Test.java [new file with mode: 0644]
bindings/java/TestArm.java [new file with mode: 0644]
bindings/java/TestArm64.java [new file with mode: 0644]
bindings/java/TestMips.java [new file with mode: 0644]
bindings/java/TestX86.java [new file with mode: 0644]
bindings/java/capstone/.gitignore [new file with mode: 0644]
bindings/java/capstone/Arm.java [new file with mode: 0644]
bindings/java/capstone/Arm64.java [new file with mode: 0644]
bindings/java/capstone/Arm64_const.java [new file with mode: 0644]
bindings/java/capstone/Arm_const.java [new file with mode: 0644]
bindings/java/capstone/Capstone.java [new file with mode: 0644]
bindings/java/capstone/Mips.java [new file with mode: 0644]
bindings/java/capstone/Mips_const.java [new file with mode: 0644]
bindings/java/capstone/X86.java [new file with mode: 0644]
bindings/java/capstone/X86_const.java [new file with mode: 0644]
bindings/java/run.sh [new file with mode: 0755]
bindings/python/Makefile [new file with mode: 0644]
bindings/python/README [new file with mode: 0644]
bindings/python/capstone/.gitignore [new file with mode: 0644]
bindings/python/capstone/__init__.py [new file with mode: 0644]
bindings/python/capstone/arm.py [new file with mode: 0644]
bindings/python/capstone/arm64.py [new file with mode: 0644]
bindings/python/capstone/arm64_const.py [new file with mode: 0644]
bindings/python/capstone/arm_const.py [new file with mode: 0644]
bindings/python/capstone/capstone.py [new file with mode: 0644]
bindings/python/capstone/mips.py [new file with mode: 0644]
bindings/python/capstone/mips_const.py [new file with mode: 0644]
bindings/python/capstone/x86.py [new file with mode: 0644]
bindings/python/capstone/x86_const.py [new file with mode: 0644]
bindings/python/setup.py [new file with mode: 0644]
bindings/python/test.py [new file with mode: 0755]
bindings/python/test_arm.py [new file with mode: 0755]
bindings/python/test_arm64.py [new file with mode: 0755]
bindings/python/test_detail.py [new file with mode: 0755]
bindings/python/test_mips.py [new file with mode: 0755]
bindings/python/test_x86.py [new file with mode: 0755]
compile.sh [new file with mode: 0755]
cs.c [new file with mode: 0644]
cs_priv.h [new file with mode: 0644]
include/arm.h [new file with mode: 0644]
include/arm64.h [new file with mode: 0644]
include/capstone.h [new file with mode: 0644]
include/mips.h [new file with mode: 0644]
include/x86.h [new file with mode: 0644]
tests/Makefile [new file with mode: 0644]
tests/README [new file with mode: 0644]
tests/test.c [new file with mode: 0644]
tests/test_arm.c [new file with mode: 0644]
tests/test_arm64.c [new file with mode: 0644]
tests/test_detail.c [new file with mode: 0644]
tests/test_mips.c [new file with mode: 0644]
tests/test_x86.c [new file with mode: 0644]
utils.c [new file with mode: 0644]
utils.h [new file with mode: 0644]

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..8e94f00
--- /dev/null
@@ -0,0 +1,41 @@
+# Object files
+*.o
+*.ko
+
+# Libraries
+*.lib
+*.a
+
+# Shared objects (inc. Windows DLLs)
+*.dll
+*.so
+*.so.*
+*.dylib
+
+# Executables
+*.exe
+*.out
+*.app
+
+# python
+bindings/python/build/
+*.pyc
+
+# java
+bindings/java/capstone.jar
+
+# test binaries
+tests/test
+tests/test_detail
+tests/test_arm
+tests/test_arm64
+tests/test_mips
+tests/test_x86
+
+# vim tmp file
+*.swp
+
+capstone.pc
+
+# local files
+_*
diff --git a/COMPILE b/COMPILE
new file mode 100644 (file)
index 0000000..0d664b8
--- /dev/null
+++ b/COMPILE
@@ -0,0 +1,82 @@
+How To Compile & Run Capstone for Linux, Mac OSX, *nix and Windows
+                        *-*-*-*-*-*
+
+
+Capstone requires no prerequisite packages, so it is easy to compile & install.
+
+
+(1) On *nix (such as MacOSX, Linux & FreeBSD):
+
+- To compile for current platform, run either:
+               $ ./compile.sh
+       or:
+               $ make
+
+       For FreeBSD/OpenBSD, use 'gmake' instread of 'make':
+
+               $ gmake
+
+       Then run "./tests/test*" to see the tests disassembling sample code.
+
+- On 64-bit OS, run command below to cross-compile Capstone for 32-bit binary:
+
+       $ ./compile.sh nix32
+
+       Then similarly, run "./tests/test*" to see the tests disassembling sample code.
+
+
+
+(2) To install Capstone, run:
+
+       $ sudo make install
+       
+       For FreeBSD/OpenBSD, use 'gmake' instead of 'make':
+
+       $ sudo gmake install
+
+Users are then required to enter root password to copy Capstone into machine
+system directories.
+
+NOTE: The core framework that will be installed by "make install" consist of
+only following files:
+
+       /usr/include/capstone/capstone.h
+       /usr/include/capstone/x86.h
+       /usr/include/capstone/arm.h
+       /usr/include/capstone/arm64.h
+       /usr/include/capstone/mips.h
+       /usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
+       /usr/lib/libcapstone.a
+
+
+
+(3) To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64
+for 64-bit binaries) are required.
+
+       - To cross-compile Windows 32-bit binary, simply run
+               $ ./compile.sh cross-win32
+
+       - To cross-compile Windows 64-bit binary, simply run
+               $ ./compile.sh cross-win64
+
+Resulted files "capstone.dll" and "tests/test*.exe" can then be used on Windows machine.
+
+
+
+(4) To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run:
+
+        - To compile Windows 32-bit binary under Cygwin, simply run
+                $ ./compile.sh cygwin-mingw32
+
+        - To compile Windows 64-bit binary under Cygwin, simply run
+                $ ./compile.sh cygwin-mingw64
+
+
+(5) By default, gcc is used as compiler. To use "clang" compiler instead, run command below:
+
+       $ ./compile.sh clang
+
+
+(6) So far, Python, Ruby, Ocaml, Java, C# and Go are supported by bindings. Look for
+the bindings under directory bindings/, and refer to README file of corresponding languages.
+
diff --git a/CONFIG b/CONFIG
new file mode 100644 (file)
index 0000000..429500a
--- /dev/null
+++ b/CONFIG
@@ -0,0 +1,6 @@
+// Package version
+
+#define PKG_MAJOR 1
+#define PKG_MINOR 0
+
+
diff --git a/CREDITS.TXT b/CREDITS.TXT
new file mode 100644 (file)
index 0000000..9c70978
--- /dev/null
@@ -0,0 +1,40 @@
+This file credits all the contributors of the Capstone engine project.
+
+Key developers
+==============
+1. Nguyen Anh Quynh <aquynh -at- gmail.com>
+       - Core engine
+       - Bindings: Python, Ruby, OCaml, Java, C#
+
+2. Tan Sheng Di <shengdi -at- coseinc.com>
+       - Bindings: Ruby
+
+3. Ben Nagy <ben -at- coseinc.com>
+       - Bindings: Ruby, Go
+
+4. Dang Hoang Vu <dang.hvu -at- gmail.com>
+       - Bindings: Java
+
+
+Beta testers (in random order)
+==============================
+Pancake
+Van Hauser
+FX of Phenoelit
+The Grugq, The Grugq   <-- our hero for submitting the first ever patch!
+Isaac Dawson, Veracode Inc
+Patroklos Argyroudis, Census Inc. (http://census-labs.com)
+Attila Suszter
+Le Dinh Long
+Nicolas Ruff
+Gunther
+Alex Ionescu, Winsider Seminars & Solutions Inc.
+Snare
+Daniel Godas-Lopez
+Joshua J. Drake
+Edgar Barbosa
+Ralf-Philipp Weinmann
+Hugo Fortier
+Joxean Koret
+Bruce Dang
+Andrew Dunham
diff --git a/HACK b/HACK
new file mode 100644 (file)
index 0000000..568d720
--- /dev/null
+++ b/HACK
@@ -0,0 +1,33 @@
+Capstone source is organized as followings.
+
+
+.                   <- core engine + README + COMPILE etc
+├── arch            <- code handling disasm engine for each arch
+│   ├── AArch64     <- ARM64 (aka ARMv8) engine
+│   ├── ARM         <- ARM engine
+│   ├── Mips        <- Mips engine
+│   └── X86         <- X86 engine
+├── bindings        <- all bindings are under this dir
+│   ├── csharp      <- C# bindings + test code
+│   ├── java        <- Java bindings + test code
+│   ├── ocaml       <- Ocaml bindings + test code
+│   ├── python      <- Python bindings + test code
+│   └── ruby        <- Ruby bindings + test code
+├── include         <- API headers in C language (*.h)
+├── release         <- Precompiled binaries
+│   ├── linux       <- .deb, .rpm, python packages, etc
+│   ├── mac         <- .dmg
+│   └── windows     <- .msi, .exe, .dll, etc
+├── tests           <- Test code (in C language)
+
+
+Follow COMPILE to see how to compile and run code.
+
+Note: if you find some strange bugs, it is recommended to firstly clean
+the code and try to recompile/reinstall again. This can be done with:
+
+       $ make clean
+       $ make
+       $ sudo make install
+
+
diff --git a/LEB128.h b/LEB128.h
new file mode 100644 (file)
index 0000000..bf555e9
--- /dev/null
+++ b/LEB128.h
@@ -0,0 +1,38 @@
+//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares some utility functions for encoding SLEB128 and
+// ULEB128 values.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_SUPPORT_LEB128_H
+#define CS_LLVM_SUPPORT_LEB128_H
+
+#include <stdint.h>
+
+/// Utility function to decode a ULEB128 value.
+static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
+{
+       const uint8_t *orig_p = p;
+       uint64_t Value = 0;
+       unsigned Shift = 0;
+       do {
+               Value += (*p & 0x7f) << Shift;
+               Shift += 7;
+       } while (*p++ >= 128);
+       if (n)
+               *n = (unsigned)(p - orig_p);
+       return Value;
+}
+
+#endif  // LLVM_SYSTEM_LEB128_H
diff --git a/LICENSE.TXT b/LICENSE.TXT
new file mode 100644 (file)
index 0000000..9edde0b
--- /dev/null
@@ -0,0 +1,30 @@
+This is the software license for Capstone disassembly framework.
+Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
+See http://www.capstone-engine.org for further information.
+
+Copyright (c) 2013, COSEINC.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+* Neither the name of the developer(s) nor the names of its
+  contributors may be used to endorse or promote products derived from this
+  software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/LICENSE_LLVM.TXT b/LICENSE_LLVM.TXT
new file mode 100644 (file)
index 0000000..66d6647
--- /dev/null
@@ -0,0 +1,71 @@
+==============================================================================
+LLVM Release License
+==============================================================================
+University of Illinois/NCSA
+Open Source License
+
+Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign.
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+==============================================================================
+Copyrights and Licenses for Third Party Software Distributed with LLVM:
+==============================================================================
+The LLVM software contains code written by third parties.  Such software will
+have its own individual LICENSE.TXT file in the directory in which it appears.
+This file will describe the copyrights, license, and restrictions which apply
+to that code.
+
+The disclaimer of warranty in the University of Illinois Open Source License
+applies to all code in the LLVM Distribution, and nothing in any of the
+other licenses gives permission to use the names of the LLVM Team or the
+University of Illinois to endorse or promote products derived from this
+Software.
+
+The following pieces of software have additional or alternate copyrights,
+licenses, and/or restrictions:
+
+Program             Directory
+-------             ---------
+Autoconf            llvm/autoconf
+                    llvm/projects/ModuleMaker/autoconf
+                    llvm/projects/sample/autoconf
+Google Test         llvm/utils/unittest/googletest
+OpenBSD regex       llvm/lib/Support/{reg*, COPYRIGHT.regex}
+pyyaml tests        llvm/test/YAMLParser/{*.data, LICENSE.TXT}
+ARM contributions   llvm/lib/Target/ARM/LICENSE.TXT
+md5 contributions   llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h
diff --git a/MCDisassembler.h b/MCDisassembler.h
new file mode 100644 (file)
index 0000000..c81ed1b
--- /dev/null
@@ -0,0 +1,14 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef __CS_MCDISASSEMBLER_H__
+#define __CS_MCDISASSEMBLER_H__ 
+
+typedef enum DecodeStatus {
+       MCDisassembler_Fail = 0,
+       MCDisassembler_SoftFail = 1,
+       MCDisassembler_Success = 3,
+} DecodeStatus;
+
+#endif
+
diff --git a/MCFixedLenDisassembler.h b/MCFixedLenDisassembler.h
new file mode 100644 (file)
index 0000000..8078a76
--- /dev/null
@@ -0,0 +1,30 @@
+//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// Fixed length disassembler decoder state machine driver.
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
+#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
+
+// Disassembler state machine opcodes.
+enum DecoderOps {
+       MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
+       MCD_OPC_FilterValue,      // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
+       MCD_OPC_CheckField,       // OPC_CheckField(uint8_t Start, uint8_t Len,
+                                                         //                uleb128 Val, uint16_t NumToSkip)
+       MCD_OPC_CheckPredicate,   // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
+       MCD_OPC_Decode,           // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
+       MCD_OPC_SoftFail,         // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
+       MCD_OPC_Fail              // OPC_Fail()
+};
+
+#endif
diff --git a/MCInst.c b/MCInst.c
new file mode 100644 (file)
index 0000000..f911257
--- /dev/null
+++ b/MCInst.c
@@ -0,0 +1,181 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "MCInst.h"
+#include "utils.h"
+
+void MCInst_Init(MCInst *inst)
+{
+       memset(inst, 0, sizeof(*inst));
+}
+
+void MCInst_clear(MCInst *inst)
+{
+       inst->size = 0;
+}
+
+// NOTE: this will free @Op argument
+void MCInst_insert(MCInst *inst, int index, MCOperand *Op)
+{
+       int i;
+
+       for(i = inst->size; i > index; i--)
+               //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
+               inst->Operands[i] = inst->Operands[i-1];
+
+       inst->Operands[index] = *Op;
+       inst->size++;
+
+       free(Op);
+}
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op)
+{
+       inst->Opcode = Op;
+}
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
+{
+       inst->OpcodePub = Op;
+}
+
+unsigned MCInst_getOpcode(const MCInst *inst)
+{
+       return inst->Opcode;
+}
+
+unsigned MCInst_getOpcodePub(const MCInst *inst)
+{
+       return inst->OpcodePub;
+}
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
+{
+       return &inst->Operands[i];
+}
+
+unsigned MCInst_getNumOperands(const MCInst *inst)
+{
+       return inst->size;
+}
+
+// NOTE: this will free @Op argument
+int MCInst_addOperand(MCInst *inst, MCOperand *Op)
+{
+       if (inst->size == ARR_SIZE(inst->Operands))
+               // full
+               return -1;
+
+       inst->Operands[inst->size] = *Op;
+       free(Op);
+
+       inst->size++;
+
+       return 0;
+}
+
+// This addOperand2 function doesnt free Op
+int MCInst_addOperand2(MCInst *inst, MCOperand *Op)
+{
+       if (inst->size == ARR_SIZE(inst->Operands))
+               // full
+               return -1;
+
+       inst->Operands[inst->size] = *Op;
+
+       inst->size++;
+
+       return 0;
+}
+
+void MCOperand_Init(MCOperand *op)
+{
+       op->Kind = kInvalid;
+       op->FPImmVal = 0.0;
+}
+
+bool MCOperand_isValid(const MCOperand *op)
+{
+       return op->Kind != kInvalid;
+}
+
+bool MCOperand_isReg(const MCOperand *op)
+{
+       return op->Kind == kRegister;
+}
+
+bool MCOperand_isImm(const MCOperand *op)
+{
+       return op->Kind == kImmediate;
+}
+
+bool MCOperand_isFPImm(const MCOperand *op)
+{
+       return op->Kind == kFPImmediate;
+}
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op)
+{
+       return op->RegVal;
+}
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg)
+{
+       op->RegVal = Reg;
+}
+
+int64_t MCOperand_getImm(MCOperand *op)
+{
+       return op->ImmVal;
+}
+
+void MCOperand_setImm(MCOperand *op, int64_t Val)
+{
+       op->ImmVal = Val;
+}
+
+double MCOperand_getFPImm(const MCOperand *op)
+{
+       return op->FPImmVal;
+}
+
+void MCOperand_setFPImm(MCOperand *op, double Val)
+{
+       op->FPImmVal = Val;
+}
+
+MCOperand *MCOperand_CreateReg(unsigned Reg)
+{
+       MCOperand *op = malloc(sizeof(*op)); 
+
+       op->Kind = kRegister;
+       op->RegVal = Reg;
+
+       return op;
+}
+
+MCOperand *MCOperand_CreateImm(int64_t Val)
+{
+       MCOperand *op = malloc(sizeof(*op)); 
+
+       op->Kind = kImmediate;
+       op->ImmVal = Val;
+
+       return op;
+}
+
+MCOperand *MCOperand_CreateFPImm(double Val)
+{
+       MCOperand *op = malloc(sizeof(*op)); 
+
+       op->Kind = kFPImmediate;
+       op->FPImmVal = Val;
+
+       return op;
+}
diff --git a/MCInst.h b/MCInst.h
new file mode 100644 (file)
index 0000000..f75a815
--- /dev/null
+++ b/MCInst.h
@@ -0,0 +1,122 @@
+//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the MCInst and MCOperand classes, which
+// is the basic representation used to represent low-level machine code
+// instructions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef __CS_MC_MCINST_H
+#define __CS_MC_MCINST_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "include/capstone.h"
+
+typedef struct MCInst MCInst;
+typedef struct MCOperand MCOperand;
+
+/// MCOperand - Instances of this class represent operands of the MCInst class.
+/// This is a simple discriminated union.
+struct MCOperand {
+       enum {
+               kInvalid = 0,                 ///< Uninitialized.
+               kRegister,                ///< Register operand.
+               kImmediate,               ///< Immediate operand.
+               kFPImmediate,             ///< Floating-point immediate operand.
+       } MachineOperandType;
+       unsigned char Kind;
+
+       union {
+               unsigned RegVal;
+               int64_t ImmVal;
+               double FPImmVal;
+       };
+};
+
+bool MCOperand_isValid(const MCOperand *op);
+
+bool MCOperand_isReg(const MCOperand *op);
+
+bool MCOperand_isImm(const MCOperand *op);
+
+bool MCOperand_isFPImm(const MCOperand *op);
+
+bool MCOperand_isInst(const MCOperand *op);
+
+void MCInst_clear(MCInst *m);
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op);
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg);
+
+int64_t MCOperand_getImm(MCOperand *op);
+
+void MCOperand_setImm(MCOperand *op, int64_t Val);
+
+double MCOperand_getFPImm(const MCOperand *op);
+
+void MCOperand_setFPImm(MCOperand *op, double Val);
+
+const MCInst *MCOperand_getInst(const MCOperand *op);
+
+void MCOperand_setInst(MCOperand *op, const MCInst *Val);
+
+MCOperand *MCOperand_CreateReg(unsigned Reg);
+
+MCOperand *MCOperand_CreateImm(int64_t Val);
+
+MCOperand *MCOperand_CreateFPImm(double Val);
+
+/// MCInst - Instances of this class represent a single low-level machine
+/// instruction.
+struct MCInst {
+       unsigned Opcode;
+       MCOperand Operands[32];
+       unsigned size;  // number of operands
+       cs_insn pub_insn;       // insn to be exposed to public
+       cs_mode mode;   // to be referenced by internal code
+       unsigned OpcodePub;
+       cs_opt_value detail;
+       int insn_size;  // instruction size
+       int x86_segment;        // remove when segment mem ref hack is redundant.
+       uint64_t address;       // address of this insn
+};
+
+void MCInst_Init(MCInst *inst);
+
+void MCInst_clear(MCInst *inst);
+
+void MCInst_insert(MCInst *inst, int index, MCOperand *Op);
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcode(const MCInst*);
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcodePub(const MCInst*);
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
+
+unsigned MCInst_getNumOperands(const MCInst *inst);
+
+int MCInst_addOperand(MCInst *inst, MCOperand *Op);
+
+// This addOperand2 function doesnt free Op
+int MCInst_addOperand2(MCInst *inst, MCOperand *Op);
+
+#endif
diff --git a/MCInstrDesc.c b/MCInstrDesc.c
new file mode 100644 (file)
index 0000000..5993323
--- /dev/null
@@ -0,0 +1,18 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include "MCInstrDesc.h"
+
+/// isPredicate - Set if this is one of the operands that made up of
+/// the predicate operand that controls an isPredicable() instruction.
+bool MCOperandInfo_isPredicate(MCOperandInfo *m)
+{
+       return m->Flags & (1 << MCOI_Predicate);
+}
+
+/// isOptionalDef - Set if this operand is a optional def.
+///
+bool MCOperandInfo_isOptionalDef(MCOperandInfo *m)
+{
+       return m->Flags & (1 << MCOI_OptionalDef);
+}
diff --git a/MCInstrDesc.h b/MCInstrDesc.h
new file mode 100644 (file)
index 0000000..4181eb3
--- /dev/null
@@ -0,0 +1,142 @@
+//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCOperandInfo and MCInstrDesc classes, which
+// are used to describe target instructions and their operands.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_MC_MCINSTRDESC_H
+#define CS_LLVM_MC_MCINSTRDESC_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+//===----------------------------------------------------------------------===//
+// Machine Operand Flags and Description
+//===----------------------------------------------------------------------===//
+
+// Operand constraints
+enum MCOI_OperandConstraint {
+       MCOI_TIED_TO = 0,    // Must be allocated the same register as.
+       MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
+};
+
+/// OperandFlags - These are flags set on operands, but should be considered
+/// private, all access should go through the MCOperandInfo accessors.
+/// See the accessors for a description of what these are.
+enum MCOI_OperandFlags {
+       MCOI_LookupPtrRegClass = 0,
+       MCOI_Predicate,
+       MCOI_OptionalDef
+};
+
+/// Operand Type - Operands are tagged with one of the values of this enum.
+enum MCOI_OperandType {
+       MCOI_OPERAND_UNKNOWN,
+       MCOI_OPERAND_IMMEDIATE,
+       MCOI_OPERAND_REGISTER,
+       MCOI_OPERAND_MEMORY,
+       MCOI_OPERAND_PCREL
+};
+
+
+/// MCOperandInfo - This holds information about one operand of a machine
+/// instruction, indicating the register class for register operands, etc.
+///
+typedef struct MCOperandInfo {
+       /// RegClass - This specifies the register class enumeration of the operand
+       /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
+       /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
+       /// get a dynamic register class.
+       int16_t RegClass;
+
+       /// Flags - These are flags from the MCOI::OperandFlags enum.
+       uint8_t Flags;
+
+       /// OperandType - Information about the type of the operand.
+       uint8_t OperandType;
+
+       /// Lower 16 bits are used to specify which constraints are set. The higher 16
+       /// bits are used to specify the value of constraints (4 bits each).
+       uint32_t Constraints;
+       /// Currently no other information.
+} MCOperandInfo;
+
+
+//===----------------------------------------------------------------------===//
+// Machine Instruction Flags and Description
+//===----------------------------------------------------------------------===//
+
+/// MCInstrDesc flags - These should be considered private to the
+/// implementation of the MCInstrDesc class.  Clients should use the predicate
+/// methods on MCInstrDesc, not use these directly.  These all correspond to
+/// bitfields in the MCInstrDesc::Flags field.
+enum {
+       MCID_Variadic = 0,
+       MCID_HasOptionalDef,
+       MCID_Pseudo,
+       MCID_Return,
+       MCID_Call,
+       MCID_Barrier,
+       MCID_Terminator,
+       MCID_Branch,
+       MCID_IndirectBranch,
+       MCID_Compare,
+       MCID_MoveImm,
+       MCID_Bitcast,
+       MCID_Select,
+       MCID_DelaySlot,
+       MCID_FoldableAsLoad,
+       MCID_MayLoad,
+       MCID_MayStore,
+       MCID_Predicable,
+       MCID_NotDuplicable,
+       MCID_UnmodeledSideEffects,
+       MCID_Commutable,
+       MCID_ConvertibleTo3Addr,
+       MCID_UsesCustomInserter,
+       MCID_HasPostISelHook,
+       MCID_Rematerializable,
+       MCID_CheapAsAMove,
+       MCID_ExtraSrcRegAllocReq,
+       MCID_ExtraDefRegAllocReq
+};
+
+/// MCInstrDesc - Describe properties that are true of each instruction in the
+/// target description file.  This captures information about side effects,
+/// register use and many other things.  There is one instance of this struct
+/// for each target instruction class, and the MachineInstr class points to
+/// this struct directly to describe itself.
+typedef struct MCInstrDesc {
+       unsigned short  Opcode;        // The opcode number
+       unsigned short  NumOperands;   // Num of args (may be more if variable_ops)
+       unsigned short  NumDefs;       // Num of args that are definitions
+       unsigned short  SchedClass;    // enum identifying instr sched class
+       unsigned short  Size;          // Number of bytes in encoding.
+       unsigned        Flags;         // Flags identifying machine instr class
+       uint64_t        TSFlags;       // Target Specific Flag values
+       uint16_t *ImplicitUses;  // Registers implicitly read by this instr
+       uint16_t *ImplicitDefs;  // Registers implicitly defined by this instr
+       MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
+       uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any     
+       // A complex method to determine is a certain is deprecated or not, and return        
+       // the reason for deprecation.
+       //bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);           
+       unsigned ComplexDeprecationInfo;        // dummy field, just to satisfy initializer
+} MCInstrDesc;
+
+bool MCOperandInfo_isPredicate(MCOperandInfo *m);
+
+bool MCOperandInfo_isOptionalDef(MCOperandInfo *m);
+
+#endif
diff --git a/MCRegisterInfo.c b/MCRegisterInfo.c
new file mode 100644 (file)
index 0000000..7b6ee1b
--- /dev/null
@@ -0,0 +1,141 @@
+//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements MCRegisterInfo functions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include "MCRegisterInfo.h"
+
+/// DiffListIterator - Base iterator class that can traverse the
+/// differentially encoded register and regunit lists in DiffLists.
+/// Don't use this class directly, use one of the specialized sub-classes
+/// defined below.
+typedef struct DiffListIterator {
+       uint16_t Val;
+       MCPhysReg *List;
+} DiffListIterator;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+               MCRegisterDesc *D, unsigned NR,
+               unsigned RA, unsigned PC,
+               MCRegisterClass *C, unsigned NC,
+               uint16_t (*RURoots)[2], unsigned NRU,
+               MCPhysReg *DL,
+               char *Strings,
+               uint16_t *SubIndices, unsigned NumIndices,
+               uint16_t *RET)
+{
+       RI->Desc = D;
+       RI->NumRegs = NR;
+       RI->RAReg = RA;
+       RI->PCReg = PC;
+       RI->Classes = C;
+       RI->DiffLists = DL;
+       RI->RegStrings = Strings;
+       RI->NumClasses = NC;
+       RI->RegUnitRoots = RURoots;
+       RI->NumRegUnits = NRU;
+       RI->SubRegIndices = SubIndices;
+       RI->NumSubRegIndices = NumIndices;
+       RI->RegEncodingTable = RET;
+}
+
+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList)
+{
+       d->Val = InitVal;
+       d->List = DiffList;
+}
+
+static uint16_t DiffListIterator_getVal(DiffListIterator *d)
+{
+       return d->Val;
+}
+
+static bool DiffListIterator_next(DiffListIterator *d)
+{
+       if (d->List == 0)
+               return false;
+
+       MCPhysReg D = *d->List;
+       d->List++;
+       d->Val += D;
+
+       if (!D)
+               d->List = 0;
+
+       return (D != 0);
+}
+
+static bool DiffListIterator_isValid(DiffListIterator *d)
+{
+       return (d->List != 0);
+}
+
+unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC)
+{
+       DiffListIterator iter;
+
+       if (Reg >= RI->NumRegs) {
+               return 0;
+       }
+
+       DiffListIterator_init(&iter, Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
+       DiffListIterator_next(&iter);
+
+       while(DiffListIterator_isValid(&iter)) {
+               uint16_t val = DiffListIterator_getVal(&iter);
+               if (MCRegisterClass_contains(RC, val) && Reg ==  MCRegisterInfo_getSubReg(RI, val, SubIdx))
+                       return val;
+
+               DiffListIterator_next(&iter);
+       }
+
+       return 0;
+}
+
+unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
+{
+       DiffListIterator iter;
+       uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
+
+       DiffListIterator_init(&iter, Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
+       DiffListIterator_next(&iter);
+
+       while(DiffListIterator_isValid(&iter)) {
+               if (*SRI == Idx)
+                       return DiffListIterator_getVal(&iter);
+               DiffListIterator_next(&iter);
+               ++SRI;
+       }
+
+       return 0;
+}
+
+MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i)
+{
+       //assert(i < getNumRegClasses() && "Register Class ID out of range");
+       if (i >= RI->NumClasses)
+               return 0;
+       return &(RI->Classes[i]);
+}
+
+bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg)
+{
+       unsigned InByte = Reg % 8;
+       unsigned Byte = Reg / 8;
+
+       if (Byte >= c->RegSetSize)
+               return false;
+
+       return (c->RegSet[Byte] & (1 << InByte)) != 0;
+}
diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h
new file mode 100644 (file)
index 0000000..b83d09d
--- /dev/null
@@ -0,0 +1,114 @@
+//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes an abstract interface used to get information about a
+// target machines register file.  This information is used for a variety of
+// purposed, especially register allocation.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_MC_MCREGISTERINFO_H
+#define CS_LLVM_MC_MCREGISTERINFO_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/// An unsigned integer type large enough to represent all physical registers,
+/// but not necessarily virtual registers.
+typedef uint16_t MCPhysReg;
+typedef MCPhysReg* iterator;
+
+typedef struct MCRegisterClass {
+       char *Name;
+       iterator RegsBegin;
+       uint8_t *RegSet;
+       uint16_t RegsSize;
+       uint16_t RegSetSize;
+       uint16_t ID;
+       uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
+       int8_t CopyCost;
+       bool Allocatable;
+} MCRegisterClass;
+
+/// MCRegisterDesc - This record contains information about a particular
+/// register.  The SubRegs field is a zero terminated array of registers that
+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
+/// of AX. The SuperRegs field is a zero terminated array of registers that are
+/// super-registers of the specific register, e.g. RAX, EAX, are
+/// super-registers of AX.
+///
+typedef struct MCRegisterDesc {
+       uint32_t Name;      // Printable name for the reg (for debugging)
+       uint32_t SubRegs;   // Sub-register set, described above
+       uint32_t SuperRegs; // Super-register set, described above
+
+       // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
+       // sub-register in SubRegs.
+       uint32_t SubRegIndices;
+
+       // RegUnits - Points to the list of register units. The low 4 bits holds the
+       // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
+       uint32_t RegUnits;
+} MCRegisterDesc;
+
+/// MCRegisterInfo base class - We assume that the target defines a static
+/// array of MCRegisterDesc objects that represent all of the machine
+/// registers that the target has.  As such, we simply have to track a pointer
+/// to this array so that we can turn register number into a register
+/// descriptor.
+///
+/// Note this class is designed to be a base class of TargetRegisterInfo, which
+/// is the interface used by codegen. However, specific targets *should never*
+/// specialize this class. MCRegisterInfo should only contain getters to access
+/// TableGen generated physical register data. It must not be extended with
+/// virtual methods.
+///
+typedef struct MCRegisterInfo {
+       MCRegisterDesc *Desc;                 // Pointer to the descriptor array
+       unsigned NumRegs;                           // Number of entries in the array
+       unsigned RAReg;                             // Return address register
+       unsigned PCReg;                             // Program counter register
+       MCRegisterClass *Classes;             // Pointer to the regclass array
+       unsigned NumClasses;                        // Number of entries in the array
+       unsigned NumRegUnits;                       // Number of regunits.
+       uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
+       MCPhysReg *DiffLists;                 // Pointer to the difflists array
+       char *RegStrings;                     // Pointer to the string table.
+       uint16_t *SubRegIndices;              // Pointer to the subreg lookup
+       // array.
+       unsigned NumSubRegIndices;                  // Number of subreg indices.
+       uint16_t *RegEncodingTable;           // Pointer to array of register
+       // encodings.
+} MCRegisterInfo;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+               MCRegisterDesc *D, unsigned NR, unsigned RA,
+               unsigned PC,
+               MCRegisterClass *C, unsigned NC,
+               uint16_t (*RURoots)[2],
+               unsigned NRU,
+               MCPhysReg *DL,
+               char *Strings,
+               uint16_t *SubIndices,
+               unsigned NumIndices,
+               uint16_t *RET);
+
+
+unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC);
+
+unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
+
+MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i);
+
+bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg);
+
+#endif
diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..bf94e86
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,113 @@
+# Capstone Disassembler Engine
+# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013>
+
+CC = $(CROSS)gcc
+AR ?= $(CROSS)ar
+RANLIB ?= $(CROSS)ranlib
+STRIP ?= $(CROSS)strip
+
+CFLAGS += -fPIC -O3 -Wall -Iinclude
+LDFLAGS += -shared
+
+PREFIX ?= /usr
+DESTDIR ?=
+INCDIR = $(DESTDIR)$(PREFIX)/include
+LIBDIR = $(DESTDIR)$(PREFIX)/lib
+
+INSTALL_DATA ?= install -m0644
+INSTALL_LIBRARY ?= install -m0755
+
+LIBNAME = capstone
+
+LIBOBJ =
+LIBOBJ += cs.o utils.o SStream.o MCInstrDesc.o MCRegisterInfo.o
+LIBOBJ += arch/Mips/MipsDisassembler.o arch/Mips/MipsInstPrinter.o arch/Mips/mapping.o
+LIBOBJ += arch/AArch64/AArch64BaseInfo.o arch/AArch64/AArch64Disassembler.o arch/AArch64/AArch64InstPrinter.o arch/AArch64/mapping.o
+LIBOBJ += arch/ARM/ARMDisassembler.o arch/ARM/ARMInstPrinter.o arch/ARM/mapping.o
+LIBOBJ += arch/X86/X86DisassemblerDecoder.o arch/X86/X86Disassembler.o arch/X86/X86IntelInstPrinter.o arch/X86/X86ATTInstPrinter.o arch/X86/mapping.o
+LIBOBJ += MCInst.o
+
+EXT = so
+AR_EXT = a
+
+# OSX?
+UNAME_S := $(shell uname -s)
+ifeq ($(UNAME_S),Darwin)
+EXT = dylib
+else
+# Cygwin?
+IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l)
+ifeq ($(IS_CYGWIN),1)
+EXT = dll
+AR_EXT = dll.a
+# Cygwin doesn't like -fPIC
+CFLAGS := $(CFLAGS:-fPIC=)
+# On Windows we need the shared library to be executable
+else
+# mingw?
+IS_MINGW := $(shell $(CC) --version | grep -i mingw | wc -l)
+ifeq ($(IS_MINGW),1)
+EXT = dll
+AR_EXT = dll.a
+# mingw doesn't like -fPIC either
+CFLAGS := $(CFLAGS:-fPIC=)
+# On Windows we need the shared library to be executable
+endif
+endif
+endif
+
+LIBRARY = lib$(LIBNAME).$(EXT)
+ARCHIVE = lib$(LIBNAME).$(AR_EXT)
+PKGCFGF = $(LIBNAME).pc
+
+VERSION=$(shell echo `grep -e PKG_MAJOR -e PKG_MINOR CONFIG | grep -v = | awk '{print $$3}'` | awk '{print $$1"."$$2}')
+
+.PHONY: all clean install uninstall
+
+all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
+       $(MAKE) -C tests
+       $(INSTALL_DATA) lib$(LIBNAME).$(EXT) tests
+
+$(LIBRARY): $(LIBOBJ)
+       $(CC) $(LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
+
+$(ARCHIVE): $(LIBOBJ)
+       rm -f $(ARCHIVE)
+       $(AR) q $(ARCHIVE) $(LIBOBJ)
+       $(RANLIB) $(ARCHIVE)
+
+$(PKGCFGF):
+       echo Name: capstone > $(PKGCFGF)
+       echo Description: Capstone disassembler engine >> $(PKGCFGF)
+       echo Version: $(VERSION) >> $(PKGCFGF)
+       echo Libs: -L$(LIBDIR) -lcapstone >> $(PKGCFGF)
+       echo Cflags: -I$(PREFIX)/include/capstone >> $(PKGCFGF)
+
+install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
+       mkdir -p $(LIBDIR)
+       $(INSTALL_LIBRARY) lib$(LIBNAME).$(EXT) $(LIBDIR)
+       $(INSTALL_DATA) lib$(LIBNAME).$(AR_EXT) $(LIBDIR)
+       mkdir -p $(INCDIR)/$(LIBNAME)
+       $(INSTALL_DATA) include/capstone.h $(INCDIR)/$(LIBNAME)
+       $(INSTALL_DATA) include/x86.h $(INCDIR)/$(LIBNAME)
+       $(INSTALL_DATA) include/arm.h $(INCDIR)/$(LIBNAME)
+       $(INSTALL_DATA) include/arm64.h $(INCDIR)/$(LIBNAME)
+       $(INSTALL_DATA) include/mips.h $(INCDIR)/$(LIBNAME)
+       mkdir -p $(LIBDIR)/pkgconfig
+       $(INSTALL_DATA) $(PKGCFGF) $(LIBDIR)/pkgconfig/
+
+uninstall:
+       rm -rf $(INCDIR)/$(LIBNAME)
+       rm -f $(LIBDIR)/lib$(LIBNAME).$(EXT)
+       rm -f $(LIBDIR)/lib$(LIBNAME).$(AR_EXT)
+       rm -f $(LIBDIR)/pkgconfig/$(LIBNAME).pc
+
+clean:
+       rm -f $(LIBOBJ) lib$(LIBNAME).*
+       #cd bindings/ruby; $(MAKE) clean; rm -rf Makefile
+       $(MAKE) -C bindings/python clean
+       $(MAKE) -C bindings/java clean
+       $(MAKE) -C tests clean
+
+.c.o:
+       $(CC) $(CFLAGS) -c $< -o $@
diff --git a/MathExtras.h b/MathExtras.h
new file mode 100644 (file)
index 0000000..98a6cb6
--- /dev/null
@@ -0,0 +1,404 @@
+//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains some functions that are useful for math stuff.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
+#define CS_LLVM_SUPPORT_MATHEXTRAS_H
+
+#include <stdint.h>
+
+#ifdef _MSC_VER
+# include <intrin.h>
+#endif
+
+// NOTE: The following support functions use the _32/_64 extensions instead of
+// type overloading so that signed and unsigned integers can be used without
+// ambiguity.
+
+/// Hi_32 - This function returns the high 32 bits of a 64 bit value.
+static inline uint32_t Hi_32(uint64_t Value) {
+       return (uint32_t)(Value >> 32);
+}
+
+/// Lo_32 - This function returns the low 32 bits of a 64 bit value.
+static inline uint32_t Lo_32(uint64_t Value) {
+       return (uint32_t)(Value);
+}
+
+/// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
+/// bit width.
+static inline bool isUIntN(unsigned N, uint64_t x) {
+       return x == (x & (~0ULL >> (64 - N)));
+}
+
+/// isIntN - Checks if an signed integer fits into the given (dynamic)
+/// bit width.
+//static inline bool isIntN(unsigned N, int64_t x) {
+//  return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
+//}
+
+/// isMask_32 - This function returns true if the argument is a sequence of ones
+/// starting at the least significant bit with the remainder zero (32 bit
+/// version).   Ex. isMask_32(0x0000FFFFU) == true.
+static inline bool isMask_32(uint32_t Value) {
+       return Value && ((Value + 1) & Value) == 0;
+}
+
+/// isMask_64 - This function returns true if the argument is a sequence of ones
+/// starting at the least significant bit with the remainder zero (64 bit
+/// version).
+static inline bool isMask_64(uint64_t Value) {
+       return Value && ((Value + 1) & Value) == 0;
+}
+
+/// isShiftedMask_32 - This function returns true if the argument contains a
+/// sequence of ones with the remainder zero (32 bit version.)
+/// Ex. isShiftedMask_32(0x0000FF00U) == true.
+static inline bool isShiftedMask_32(uint32_t Value) {
+       return isMask_32((Value - 1) | Value);
+}
+
+/// isShiftedMask_64 - This function returns true if the argument contains a
+/// sequence of ones with the remainder zero (64 bit version.)
+static inline bool isShiftedMask_64(uint64_t Value) {
+       return isMask_64((Value - 1) | Value);
+}
+
+/// isPowerOf2_32 - This function returns true if the argument is a power of
+/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
+static inline bool isPowerOf2_32(uint32_t Value) {
+       return Value && !(Value & (Value - 1));
+}
+
+/// CountLeadingZeros_32 - this function performs the platform optimal form of
+/// counting the number of zeros from the most significant bit to the first one
+/// bit.  Ex. CountLeadingZeros_32(0x00F000FF) == 8.
+/// Returns 32 if the word is zero.
+static inline unsigned CountLeadingZeros_32(uint32_t Value) {
+       unsigned Count; // result
+#if __GNUC__ >= 4
+       // PowerPC is defined for __builtin_clz(0)
+#if !defined(__ppc__) && !defined(__ppc64__)
+       if (!Value) return 32;
+#endif
+       Count = __builtin_clz(Value);
+#else
+       if (!Value) return 32;
+       Count = 0;
+       // bisection method for count leading zeros
+       for (unsigned Shift = 32 >> 1; Shift; Shift >>= 1) {
+               uint32_t Tmp = Value >> Shift;
+               if (Tmp) {
+                       Value = Tmp;
+               } else {
+                       Count |= Shift;
+               }
+       }
+#endif
+       return Count;
+}
+
+/// CountLeadingOnes_32 - this function performs the operation of
+/// counting the number of ones from the most significant bit to the first zero
+/// bit.  Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
+/// Returns 32 if the word is all ones.
+static inline unsigned CountLeadingOnes_32(uint32_t Value) {
+       return CountLeadingZeros_32(~Value);
+}
+
+/// CountLeadingZeros_64 - This function performs the platform optimal form
+/// of counting the number of zeros from the most significant bit to the first
+/// one bit (64 bit edition.)
+/// Returns 64 if the word is zero.
+static inline unsigned CountLeadingZeros_64(uint64_t Value) {
+       unsigned Count; // result
+#if __GNUC__ >= 4
+       // PowerPC is defined for __builtin_clzll(0)
+#if !defined(__ppc__) && !defined(__ppc64__)
+       if (!Value) return 64;
+#endif
+       Count = __builtin_clzll(Value);
+#else
+       if (sizeof(long) == sizeof(int64_t)) {
+               if (!Value) return 64;
+               Count = 0;
+               // bisection method for count leading zeros
+               for (unsigned Shift = 64 >> 1; Shift; Shift >>= 1) {
+                       uint64_t Tmp = Value >> Shift;
+                       if (Tmp) {
+                               Value = Tmp;
+                       } else {
+                               Count |= Shift;
+                       }
+               }
+       } else {
+               // get hi portion
+               uint32_t Hi = Hi_32(Value);
+
+               // if some bits in hi portion
+               if (Hi) {
+                       // leading zeros in hi portion plus all bits in lo portion
+                       Count = CountLeadingZeros_32(Hi);
+               } else {
+                       // get lo portion
+                       uint32_t Lo = Lo_32(Value);
+                       // same as 32 bit value
+                       Count = CountLeadingZeros_32(Lo)+32;
+               }
+       }
+#endif
+       return Count;
+}
+
+/// CountLeadingOnes_64 - This function performs the operation
+/// of counting the number of ones from the most significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+static inline unsigned CountLeadingOnes_64(uint64_t Value) {
+       return CountLeadingZeros_64(~Value);
+}
+
+/// CountTrailingZeros_32 - this function performs the platform optimal form of
+/// counting the number of zeros from the least significant bit to the first one
+/// bit.  Ex. CountTrailingZeros_32(0xFF00FF00) == 8.
+/// Returns 32 if the word is zero.
+static inline unsigned CountTrailingZeros_32(uint32_t Value) {
+#if __GNUC__ >= 4
+       return Value ? __builtin_ctz(Value) : 32;
+#else
+       static const unsigned Mod37BitPosition[] = {
+               32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
+               4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
+               5, 20, 8, 19, 18
+       };
+       // Replace "-Value" by "1+~Value" in the following commented code to avoid 
+       // MSVC warning C4146
+       //    return Mod37BitPosition[(-Value & Value) % 37];
+       return Mod37BitPosition[((1 + ~Value) & Value) % 37];
+#endif
+}
+
+/// CountTrailingOnes_32 - this function performs the operation of
+/// counting the number of ones from the least significant bit to the first zero
+/// bit.  Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
+/// Returns 32 if the word is all ones.
+static inline unsigned CountTrailingOnes_32(uint32_t Value) {
+       return CountTrailingZeros_32(~Value);
+}
+
+/// CountTrailingZeros_64 - This function performs the platform optimal form
+/// of counting the number of zeros from the least significant bit to the first
+/// one bit (64 bit edition.)
+/// Returns 64 if the word is zero.
+static inline unsigned CountTrailingZeros_64(uint64_t Value) {
+#if __GNUC__ >= 4
+       return Value ? __builtin_ctzll(Value) : 64;
+#else
+       static const unsigned Mod67Position[] = {
+               64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
+               4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
+               47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
+               29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
+               7, 48, 35, 6, 34, 33, 0
+       };
+       // Replace "-Value" by "1+~Value" in the following commented code to avoid 
+       // MSVC warning C4146
+       //    return Mod67Position[(-Value & Value) % 67];
+       return Mod67Position[((1 + ~Value) & Value) % 67];
+#endif
+}
+
+/// CountTrailingOnes_64 - This function performs the operation
+/// of counting the number of ones from the least significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+static inline unsigned CountTrailingOnes_64(uint64_t Value) {
+       return CountTrailingZeros_64(~Value);
+}
+
+/// CountPopulation_32 - this function counts the number of set bits in a value.
+/// Ex. CountPopulation(0xF000F000) = 8
+/// Returns 0 if the word is zero.
+static inline unsigned CountPopulation_32(uint32_t Value) {
+#if __GNUC__ >= 4
+       return __builtin_popcount(Value);
+#else
+       uint32_t v = Value - ((Value >> 1) & 0x55555555);
+       v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
+       return ((v + (v >> 4) & 0xF0F0F0F) * 0x1010101) >> 24;
+#endif
+}
+
+/// CountPopulation_64 - this function counts the number of set bits in a value,
+/// (64 bit edition.)
+static inline unsigned CountPopulation_64(uint64_t Value) {
+#if __GNUC__ >= 4
+       return __builtin_popcountll(Value);
+#else
+       uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
+       v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
+       v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
+       return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56);
+#endif
+}
+
+/// Log2_32 - This function returns the floor log base 2 of the specified value,
+/// -1 if the value is zero. (32 bit edition.)
+/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
+static inline unsigned Log2_32(uint32_t Value) {
+       return 31 - CountLeadingZeros_32(Value);
+}
+
+/// Log2_64 - This function returns the floor log base 2 of the specified value,
+/// -1 if the value is zero. (64 bit edition.)
+static inline unsigned Log2_64(uint64_t Value) {
+       return 63 - CountLeadingZeros_64(Value);
+}
+
+/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified
+/// value, 32 if the value is zero. (32 bit edition).
+/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
+static inline unsigned Log2_32_Ceil(uint32_t Value) {
+       return 32-CountLeadingZeros_32(Value-1);
+}
+
+/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified
+/// value, 64 if the value is zero. (64 bit edition.)
+static inline unsigned Log2_64_Ceil(uint64_t Value) {
+       return 64-CountLeadingZeros_64(Value-1);
+}
+
+/// GreatestCommonDivisor64 - Return the greatest common divisor of the two
+/// values using Euclid's algorithm.
+static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
+       while (B) {
+               uint64_t T = B;
+               B = A % B;
+               A = T;
+       }
+       return A;
+}
+
+/// BitsToDouble - This function takes a 64-bit integer and returns the bit
+/// equivalent double.
+static inline double BitsToDouble(uint64_t Bits) {
+       union {
+               uint64_t L;
+               double D;
+       } T;
+       T.L = Bits;
+       return T.D;
+}
+
+/// BitsToFloat - This function takes a 32-bit integer and returns the bit
+/// equivalent float.
+static inline float BitsToFloat(uint32_t Bits) {
+       union {
+               uint32_t I;
+               float F;
+       } T;
+       T.I = Bits;
+       return T.F;
+}
+
+/// DoubleToBits - This function takes a double and returns the bit
+/// equivalent 64-bit integer.  Note that copying doubles around
+/// changes the bits of NaNs on some hosts, notably x86, so this
+/// routine cannot be used if these bits are needed.
+static inline uint64_t DoubleToBits(double Double) {
+       union {
+               uint64_t L;
+               double D;
+       } T;
+       T.D = Double;
+       return T.L;
+}
+
+/// FloatToBits - This function takes a float and returns the bit
+/// equivalent 32-bit integer.  Note that copying floats around
+/// changes the bits of NaNs on some hosts, notably x86, so this
+/// routine cannot be used if these bits are needed.
+static inline uint32_t FloatToBits(float Float) {
+       union {
+               uint32_t I;
+               float F;
+       } T;
+       T.F = Float;
+       return T.I;
+}
+
+/// MinAlign - A and B are either alignments or offsets.  Return the minimum
+/// alignment that may be assumed after adding the two together.
+static inline uint64_t MinAlign(uint64_t A, uint64_t B) {
+       // The largest power of 2 that divides both A and B.
+       //
+       // Replace "-Value" by "1+~Value" in the following commented code to avoid 
+       // MSVC warning C4146
+       //    return (A | B) & -(A | B);
+       return (A | B) & (1 + ~(A | B));
+}
+
+/// NextPowerOf2 - Returns the next power of two (in 64-bits)
+/// that is strictly greater than A.  Returns zero on overflow.
+static inline uint64_t NextPowerOf2(uint64_t A) {
+       A |= (A >> 1);
+       A |= (A >> 2);
+       A |= (A >> 4);
+       A |= (A >> 8);
+       A |= (A >> 16);
+       A |= (A >> 32);
+       return A + 1;
+}
+
+/// Returns the next integer (mod 2**64) that is greater than or equal to
+/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
+///
+/// Examples:
+/// \code
+///   RoundUpToAlignment(5, 8) = 8
+///   RoundUpToAlignment(17, 8) = 24
+///   RoundUpToAlignment(~0LL, 8) = 0
+/// \endcode
+static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
+       return ((Value + Align - 1) / Align) * Align;
+}
+
+/// Returns the offset to the next integer (mod 2**64) that is greater than
+/// or equal to \p Value and is a multiple of \p Align. \p Align must be
+/// non-zero.
+static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
+       return RoundUpToAlignment(Value, Align) - Value;
+}
+
+/// abs64 - absolute value of a 64-bit int.  Not all environments support
+/// "abs" on whatever their name for the 64-bit int type is.  The absolute
+/// value of the largest negative number is undefined, as with "abs".
+static inline int64_t abs64(int64_t x) {
+       return (x < 0) ? -x : x;
+}
+
+/// \brief Sign extend number in the bottom B bits of X to a 32-bit int.
+/// Requires 0 < B <= 32.
+static inline int32_t SignExtend32(uint32_t X, unsigned B) {
+       return (int32_t)(X << (32 - B)) >> (32 - B);
+}
+
+/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
+/// Requires 0 < B <= 64.
+static inline int64_t SignExtend64(uint64_t X, unsigned B) {
+       return (int64_t)(X << (64 - B)) >> (64 - B);
+}
+
+#endif
diff --git a/README b/README
new file mode 100644 (file)
index 0000000..eefc86f
--- /dev/null
+++ b/README
@@ -0,0 +1,54 @@
+Capstone is a disassembly framework with the target of becoming the ultimate
+disasm engine for binary analysis and reversing in the security community.
+
+Created by Nguyen Anh Quynh, then developed and maintained by a small community,
+Capstone offers some unparalleled features:
+
+- Support multiple hardware architectures: ARM, ARM64 (aka ARMv8), Mips & X86.
+
+- Having clean/simple/lightweight/intuitive architecture-neutral API.
+
+- Provide details on disassembled instruction (called “decomposer” by others).
+
+- Provide semantics of the disassembled instruction, such as list of implicit
+     registers read & written.
+
+- Implemented in pure C language, with lightweight wrappers for C++, Python,
+     Ruby, OCaml, C#, Java and Go available.
+
+- Native support for Windows & *nix platforms (MacOSX, Linux & *BSD confirmed).
+
+- Thread-safe by design.
+
+- Distributed under the open source BSD license.
+
+Further information is available at http://www.capstone-engine.org
+
+
+[Compile]
+
+See COMPILE file for how to compile and install Capstone
+
+
+[Status]
+
+- Capstone can only compile to Windows via Cygwin, or cross-compile using
+MingW. Visual Studio support will be done in the future.
+
+- X86 engine cannot handle many malware tricks yet. Please report all the raw
+binary code that Capstone cannot disassemble, or does that wrongly, so we can
+fix that in the next version
+
+- This package only contains Java & Python bindings. For C#, Go, Ocaml & Ruby,
+refer to the corresponding git repositories.
+
+
+[Hack]
+
+See HACK file for the structuture of the source code.
+
+
+[License]
+
+This project is released under the BSD license. If you redistribute the binary
+or source code of Capstone, please attach file LICENSE.TXT with your products.
diff --git a/SStream.c b/SStream.c
new file mode 100644 (file)
index 0000000..e6678ad
--- /dev/null
+++ b/SStream.c
@@ -0,0 +1,45 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdint.h>
+#include <stdarg.h>
+#include <stdio.h>
+
+#include "SStream.h"
+
+void SStream_Init(SStream *ss)
+{
+       ss->index = 0;
+       ss->buffer[0] = '\0';
+}
+
+void SStream_concat(SStream *ss, const char *fmt, ...)
+{
+       va_list ap;
+
+       va_start(ap, fmt);
+       int ret = vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
+       va_end(ap);
+       ss->index += ret;
+}
+
+/*
+   int main()
+   {
+   SStream ss;
+   int64_t i;
+
+   SStream_Init(&ss);
+
+   SStream_concat(&ss, "hello ");
+   SStream_concat(&ss, "%d - 0x%x", 200, 16);
+
+   i = 123;
+   SStream_concat(&ss, " + %ld", i);
+   SStream_concat(&ss, "%s", "haaaaa");
+
+   printf("%s\n", ss.buffer);
+
+   return 0;
+   }
+ */
diff --git a/SStream.h b/SStream.h
new file mode 100644 (file)
index 0000000..e893453
--- /dev/null
+++ b/SStream.h
@@ -0,0 +1,16 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_SSTREAM_H_
+#define CS_SSTREAM_H_
+
+typedef struct SStream {
+       char buffer[512];
+       int index;
+} SStream;
+
+void SStream_Init(SStream *ss);
+
+void SStream_concat(SStream *ss, const char *fmt, ...);
+
+#endif
diff --git a/SubtargetFeature.h b/SubtargetFeature.h
new file mode 100644 (file)
index 0000000..649fad8
--- /dev/null
@@ -0,0 +1,36 @@
+//===-- llvm/MC/SubtargetFeature.h - CPU characteristics --------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines and manages user or tool specified CPU characteristics.
+// The intent is to be able to package specific features that should or should
+// not be used on a specific target processor.  A tool, such as llc, could, as
+// as example, gather chip info from the command line, a long with features
+// that should be used on that chip.
+//
+//===----------------------------------------------------------------------===//
+
+/* Second-Best Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_MC_SUBTARGETFEATURE_H
+#define CS_LLVM_MC_SUBTARGETFEATURE_H
+
+//===----------------------------------------------------------------------===//
+///
+/// SubtargetFeatureKV - Used to provide key value pairs for feature and
+/// CPU bit flags.
+//
+typedef struct SubtargetFeatureKV {
+  char *Key;                      // K-V key string
+  char *Desc;                     // Help descriptor
+  const uint64_t Value;                 // K-V integer value
+  const uint64_t Implies;               // K-V bit mask
+} SubtargetFeatureKV;
+
+#endif
diff --git a/TODO b/TODO
new file mode 100644 (file)
index 0000000..6b61ac8
--- /dev/null
+++ b/TODO
@@ -0,0 +1,23 @@
+Issues to be solved in next versions
+
+
+[Core]
+
+- X86 cannot handle many tricks introduced by malware yet. If you find any such
+  instruction sequence that Capstone disassembles wrongly or fails completely,
+  please report. This would be the top priority of our project.
+
+- More optimization for better performance.
+
+- Support more operand details for Arm, Arm64, Mips & X86, especially focus on
+  non-standard instructions.
+
+- At the moment the only way to get Windows binaries is cross-compiling. We have
+  to port the code over to Visual Studio, so those only have Windows can still
+  compile Capstone without needing to have Linux machine for cross-compiling.
+
+[Bindings]
+
+- OCaml & C# bindings are broken due to many API changes. This should be fixed ASAP.
+
+- Python 3 support is needed.
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
new file mode 100644 (file)
index 0000000..1b9ead0
--- /dev/null
@@ -0,0 +1,982 @@
+//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for AArch64.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include "../../utils.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "AArch64BaseInfo.h"
+
+char *NamedImmMapper_toString(NamedImmMapper *N, uint32_t Value, bool *Valid)
+{
+       unsigned i;
+       for (i = 0; i < N->NumPairs; ++i) {
+               if (N->Pairs[i].Value == Value) {
+                       *Valid = true;
+                       return N->Pairs[i].Name;
+               }
+       }
+
+       *Valid = false;
+       return 0;
+}
+
+// compare s1 with lower(s2)
+// return true if s1 == lower(f2), and false otherwise
+static bool compare_lower_str(char *s1, char *s2)
+{
+       char *lower = strdup(s2), *c;
+       for (c = lower; *c; c++)
+               *c = tolower((int) *c);
+
+       bool res = (strcmp(s1, lower) == 0);
+       free(lower);
+
+       return res;
+}
+
+uint32_t NamedImmMapper_fromString(NamedImmMapper *N, char *Name, bool *Valid)
+{
+       unsigned i;
+       for (i = 0; i < N->NumPairs; ++i) {
+               if (compare_lower_str(N->Pairs[i].Name, Name)) {
+                       *Valid = true;
+                       return N->Pairs[i].Value;
+               }
+       }
+
+       *Valid = false;
+       return -1;
+}
+
+bool NamedImmMapper_validImm(NamedImmMapper *N, uint32_t Value)
+{
+       return Value < N->TooBigImm;
+}
+
+// return a string representing the number X
+// NOTE: caller must free() the result itself to avoid memory leak
+static char *utostr(uint64_t X, bool isNeg)
+{
+       char Buffer[22];
+       char *BufPtr = Buffer+21;
+
+       Buffer[21] = '\0';
+       if (X == 0) *--BufPtr = '0';  // Handle special case...
+
+       while (X) {
+               *--BufPtr = X % 10 + '0';
+               X /= 10;
+       }
+
+       if (isNeg) *--BufPtr = '-';   // Add negative sign...
+
+       char *result = strdup(BufPtr);
+       return result;
+}
+
+static NamedImmMapper_Mapping SysRegPairs[] = {
+       {"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
+       {"osdtrtx_el1",  A64SysReg_OSDTRTX_EL1},
+       {"teecr32_el1", A64SysReg_TEECR32_EL1},
+       {"mdccint_el1", A64SysReg_MDCCINT_EL1},
+       {"mdscr_el1", A64SysReg_MDSCR_EL1},
+       {"dbgdtr_el0", A64SysReg_DBGDTR_EL0},
+       {"oseccr_el1", A64SysReg_OSECCR_EL1},
+       {"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2},
+       {"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1},
+       {"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1},
+       {"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1},
+       {"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1},
+       {"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1},
+       {"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1},
+       {"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1},
+       {"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1},
+       {"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1},
+       {"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1},
+       {"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1},
+       {"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1},
+       {"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1},
+       {"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1},
+       {"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1},
+       {"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1},
+       {"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1},
+       {"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1},
+       {"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1},
+       {"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1},
+       {"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1},
+       {"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1},
+       {"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1},
+       {"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1},
+       {"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1},
+       {"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1},
+       {"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1},
+       {"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1},
+       {"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1},
+       {"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1},
+       {"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1},
+       {"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1},
+       {"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1},
+       {"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1},
+       {"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1},
+       {"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1},
+       {"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1},
+       {"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1},
+       {"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1},
+       {"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1},
+       {"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1},
+       {"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1},
+       {"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1},
+       {"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1},
+       {"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1},
+       {"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1},
+       {"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1},
+       {"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1},
+       {"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1},
+       {"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1},
+       {"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1},
+       {"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1},
+       {"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1},
+       {"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1},
+       {"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1},
+       {"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1},
+       {"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1},
+       {"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1},
+       {"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1},
+       {"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1},
+       {"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1},
+       {"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1},
+       {"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1},
+       {"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1},
+       {"teehbr32_el1", A64SysReg_TEEHBR32_EL1},
+       {"osdlr_el1", A64SysReg_OSDLR_EL1},
+       {"dbgprcr_el1", A64SysReg_DBGPRCR_EL1},
+       {"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1},
+       {"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1},
+       {"csselr_el1", A64SysReg_CSSELR_EL1},
+       {"vpidr_el2", A64SysReg_VPIDR_EL2},
+       {"vmpidr_el2", A64SysReg_VMPIDR_EL2},
+       {"sctlr_el1", A64SysReg_SCTLR_EL1},
+       {"sctlr_el2", A64SysReg_SCTLR_EL2},
+       {"sctlr_el3", A64SysReg_SCTLR_EL3},
+       {"actlr_el1", A64SysReg_ACTLR_EL1},
+       {"actlr_el2", A64SysReg_ACTLR_EL2},
+       {"actlr_el3", A64SysReg_ACTLR_EL3},
+       {"cpacr_el1", A64SysReg_CPACR_EL1},
+       {"hcr_el2", A64SysReg_HCR_EL2},
+       {"scr_el3", A64SysReg_SCR_EL3},
+       {"mdcr_el2", A64SysReg_MDCR_EL2},
+       {"sder32_el3", A64SysReg_SDER32_EL3},
+       {"cptr_el2", A64SysReg_CPTR_EL2},
+       {"cptr_el3", A64SysReg_CPTR_EL3},
+       {"hstr_el2", A64SysReg_HSTR_EL2},
+       {"hacr_el2", A64SysReg_HACR_EL2},
+       {"mdcr_el3", A64SysReg_MDCR_EL3},
+       {"ttbr0_el1", A64SysReg_TTBR0_EL1},
+       {"ttbr0_el2", A64SysReg_TTBR0_EL2},
+       {"ttbr0_el3", A64SysReg_TTBR0_EL3},
+       {"ttbr1_el1", A64SysReg_TTBR1_EL1},
+       {"tcr_el1", A64SysReg_TCR_EL1},
+       {"tcr_el2", A64SysReg_TCR_EL2},
+       {"tcr_el3", A64SysReg_TCR_EL3},
+       {"vttbr_el2", A64SysReg_VTTBR_EL2},
+       {"vtcr_el2", A64SysReg_VTCR_EL2},
+       {"dacr32_el2", A64SysReg_DACR32_EL2},
+       {"spsr_el1", A64SysReg_SPSR_EL1},
+       {"spsr_el2", A64SysReg_SPSR_EL2},
+       {"spsr_el3", A64SysReg_SPSR_EL3},
+       {"elr_el1", A64SysReg_ELR_EL1},
+       {"elr_el2", A64SysReg_ELR_EL2},
+       {"elr_el3", A64SysReg_ELR_EL3},
+       {"sp_el0", A64SysReg_SP_EL0},
+       {"sp_el1", A64SysReg_SP_EL1},
+       {"sp_el2", A64SysReg_SP_EL2},
+       {"spsel", A64SysReg_SPSel},
+       {"nzcv", A64SysReg_NZCV},
+       {"daif", A64SysReg_DAIF},
+       {"currentel", A64SysReg_CurrentEL},
+       {"spsr_irq", A64SysReg_SPSR_irq},
+       {"spsr_abt", A64SysReg_SPSR_abt},
+       {"spsr_und", A64SysReg_SPSR_und},
+       {"spsr_fiq", A64SysReg_SPSR_fiq},
+       {"fpcr", A64SysReg_FPCR},
+       {"fpsr", A64SysReg_FPSR},
+       {"dspsr_el0", A64SysReg_DSPSR_EL0},
+       {"dlr_el0", A64SysReg_DLR_EL0},
+       {"ifsr32_el2", A64SysReg_IFSR32_EL2},
+       {"afsr0_el1", A64SysReg_AFSR0_EL1},
+       {"afsr0_el2", A64SysReg_AFSR0_EL2},
+       {"afsr0_el3", A64SysReg_AFSR0_EL3},
+       {"afsr1_el1", A64SysReg_AFSR1_EL1},
+       {"afsr1_el2", A64SysReg_AFSR1_EL2},
+       {"afsr1_el3", A64SysReg_AFSR1_EL3},
+       {"esr_el1", A64SysReg_ESR_EL1},
+       {"esr_el2", A64SysReg_ESR_EL2},
+       {"esr_el3", A64SysReg_ESR_EL3},
+       {"fpexc32_el2", A64SysReg_FPEXC32_EL2},
+       {"far_el1", A64SysReg_FAR_EL1},
+       {"far_el2", A64SysReg_FAR_EL2},
+       {"far_el3", A64SysReg_FAR_EL3},
+       {"hpfar_el2", A64SysReg_HPFAR_EL2},
+       {"par_el1", A64SysReg_PAR_EL1},
+       {"pmcr_el0", A64SysReg_PMCR_EL0},
+       {"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0},
+       {"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0},
+       {"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0},
+       {"pmselr_el0", A64SysReg_PMSELR_EL0},
+       {"pmccntr_el0", A64SysReg_PMCCNTR_EL0},
+       {"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0},
+       {"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0},
+       {"pmuserenr_el0", A64SysReg_PMUSERENR_EL0},
+       {"pmintenset_el1", A64SysReg_PMINTENSET_EL1},
+       {"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
+       {"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
+       {"mair_el1", A64SysReg_MAIR_EL1},
+       {"mair_el2", A64SysReg_MAIR_EL2},
+       {"mair_el3", A64SysReg_MAIR_EL3},
+       {"amair_el1", A64SysReg_AMAIR_EL1},
+       {"amair_el2", A64SysReg_AMAIR_EL2},
+       {"amair_el3", A64SysReg_AMAIR_EL3},
+       {"vbar_el1", A64SysReg_VBAR_EL1},
+       {"vbar_el2", A64SysReg_VBAR_EL2},
+       {"vbar_el3", A64SysReg_VBAR_EL3},
+       {"rmr_el1", A64SysReg_RMR_EL1},
+       {"rmr_el2", A64SysReg_RMR_EL2},
+       {"rmr_el3", A64SysReg_RMR_EL3},
+       {"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
+       {"tpidr_el0", A64SysReg_TPIDR_EL0},
+       {"tpidr_el2", A64SysReg_TPIDR_EL2},
+       {"tpidr_el3", A64SysReg_TPIDR_EL3},
+       {"tpidrro_el0", A64SysReg_TPIDRRO_EL0},
+       {"tpidr_el1", A64SysReg_TPIDR_EL1},
+       {"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
+       {"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
+       {"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
+       {"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
+       {"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
+       {"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
+       {"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
+       {"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
+       {"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
+       {"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
+       {"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
+       {"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
+       {"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
+       {"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
+       {"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
+       {"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
+       {"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
+       {"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
+       {"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
+       {"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0},
+       {"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0},
+       {"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0},
+       {"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0},
+       {"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0},
+       {"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0},
+       {"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0},
+       {"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0},
+       {"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0},
+       {"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0},
+       {"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0},
+       {"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0},
+       {"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0},
+       {"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0},
+       {"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0},
+       {"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0},
+       {"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0},
+       {"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0},
+       {"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0},
+       {"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0},
+       {"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0},
+       {"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0},
+       {"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0},
+       {"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0},
+       {"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0},
+       {"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0},
+       {"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0},
+       {"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0},
+       {"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0},
+       {"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0},
+       {"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0},
+       {"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0},
+       {"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0},
+       {"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0},
+       {"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0},
+       {"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0},
+       {"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0},
+       {"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0},
+       {"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0},
+       {"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0},
+       {"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0},
+       {"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0},
+       {"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0},
+       {"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0},
+       {"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0},
+       {"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0},
+       {"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0},
+       {"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0},
+       {"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0},
+       {"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0},
+       {"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0},
+       {"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0},
+       {"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0},
+       {"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0},
+       {"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0},
+       {"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0},
+       {"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0},
+       {"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
+       {"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
+       {"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
+
+       // Trace registers
+       {"trcprgctlr", A64SysReg_TRCPRGCTLR},
+       {"trcprocselr", A64SysReg_TRCPROCSELR},
+       {"trcconfigr", A64SysReg_TRCCONFIGR},
+       {"trcauxctlr", A64SysReg_TRCAUXCTLR},
+       {"trceventctl0r", A64SysReg_TRCEVENTCTL0R},
+       {"trceventctl1r", A64SysReg_TRCEVENTCTL1R},
+       {"trcstallctlr", A64SysReg_TRCSTALLCTLR},
+       {"trctsctlr", A64SysReg_TRCTSCTLR},
+       {"trcsyncpr", A64SysReg_TRCSYNCPR},
+       {"trcccctlr", A64SysReg_TRCCCCTLR},
+       {"trcbbctlr", A64SysReg_TRCBBCTLR},
+       {"trctraceidr", A64SysReg_TRCTRACEIDR},
+       {"trcqctlr", A64SysReg_TRCQCTLR},
+       {"trcvictlr", A64SysReg_TRCVICTLR},
+       {"trcviiectlr", A64SysReg_TRCVIIECTLR},
+       {"trcvissctlr", A64SysReg_TRCVISSCTLR},
+       {"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR},
+       {"trcvdctlr", A64SysReg_TRCVDCTLR},
+       {"trcvdsacctlr", A64SysReg_TRCVDSACCTLR},
+       {"trcvdarcctlr", A64SysReg_TRCVDARCCTLR},
+       {"trcseqevr0", A64SysReg_TRCSEQEVR0},
+       {"trcseqevr1", A64SysReg_TRCSEQEVR1},
+       {"trcseqevr2", A64SysReg_TRCSEQEVR2},
+       {"trcseqrstevr", A64SysReg_TRCSEQRSTEVR},
+       {"trcseqstr", A64SysReg_TRCSEQSTR},
+       {"trcextinselr", A64SysReg_TRCEXTINSELR},
+       {"trccntrldvr0", A64SysReg_TRCCNTRLDVR0},
+       {"trccntrldvr1", A64SysReg_TRCCNTRLDVR1},
+       {"trccntrldvr2", A64SysReg_TRCCNTRLDVR2},
+       {"trccntrldvr3", A64SysReg_TRCCNTRLDVR3},
+       {"trccntctlr0", A64SysReg_TRCCNTCTLR0},
+       {"trccntctlr1", A64SysReg_TRCCNTCTLR1},
+       {"trccntctlr2", A64SysReg_TRCCNTCTLR2},
+       {"trccntctlr3", A64SysReg_TRCCNTCTLR3},
+       {"trccntvr0", A64SysReg_TRCCNTVR0},
+       {"trccntvr1", A64SysReg_TRCCNTVR1},
+       {"trccntvr2", A64SysReg_TRCCNTVR2},
+       {"trccntvr3", A64SysReg_TRCCNTVR3},
+       {"trcimspec0", A64SysReg_TRCIMSPEC0},
+       {"trcimspec1", A64SysReg_TRCIMSPEC1},
+       {"trcimspec2", A64SysReg_TRCIMSPEC2},
+       {"trcimspec3", A64SysReg_TRCIMSPEC3},
+       {"trcimspec4", A64SysReg_TRCIMSPEC4},
+       {"trcimspec5", A64SysReg_TRCIMSPEC5},
+       {"trcimspec6", A64SysReg_TRCIMSPEC6},
+       {"trcimspec7", A64SysReg_TRCIMSPEC7},
+       {"trcrsctlr2", A64SysReg_TRCRSCTLR2},
+       {"trcrsctlr3", A64SysReg_TRCRSCTLR3},
+       {"trcrsctlr4", A64SysReg_TRCRSCTLR4},
+       {"trcrsctlr5", A64SysReg_TRCRSCTLR5},
+       {"trcrsctlr6", A64SysReg_TRCRSCTLR6},
+       {"trcrsctlr7", A64SysReg_TRCRSCTLR7},
+       {"trcrsctlr8", A64SysReg_TRCRSCTLR8},
+       {"trcrsctlr9", A64SysReg_TRCRSCTLR9},
+       {"trcrsctlr10", A64SysReg_TRCRSCTLR10},
+       {"trcrsctlr11", A64SysReg_TRCRSCTLR11},
+       {"trcrsctlr12", A64SysReg_TRCRSCTLR12},
+       {"trcrsctlr13", A64SysReg_TRCRSCTLR13},
+       {"trcrsctlr14", A64SysReg_TRCRSCTLR14},
+       {"trcrsctlr15", A64SysReg_TRCRSCTLR15},
+       {"trcrsctlr16", A64SysReg_TRCRSCTLR16},
+       {"trcrsctlr17", A64SysReg_TRCRSCTLR17},
+       {"trcrsctlr18", A64SysReg_TRCRSCTLR18},
+       {"trcrsctlr19", A64SysReg_TRCRSCTLR19},
+       {"trcrsctlr20", A64SysReg_TRCRSCTLR20},
+       {"trcrsctlr21", A64SysReg_TRCRSCTLR21},
+       {"trcrsctlr22", A64SysReg_TRCRSCTLR22},
+       {"trcrsctlr23", A64SysReg_TRCRSCTLR23},
+       {"trcrsctlr24", A64SysReg_TRCRSCTLR24},
+       {"trcrsctlr25", A64SysReg_TRCRSCTLR25},
+       {"trcrsctlr26", A64SysReg_TRCRSCTLR26},
+       {"trcrsctlr27", A64SysReg_TRCRSCTLR27},
+       {"trcrsctlr28", A64SysReg_TRCRSCTLR28},
+       {"trcrsctlr29", A64SysReg_TRCRSCTLR29},
+       {"trcrsctlr30", A64SysReg_TRCRSCTLR30},
+       {"trcrsctlr31", A64SysReg_TRCRSCTLR31},
+       {"trcssccr0", A64SysReg_TRCSSCCR0},
+       {"trcssccr1", A64SysReg_TRCSSCCR1},
+       {"trcssccr2", A64SysReg_TRCSSCCR2},
+       {"trcssccr3", A64SysReg_TRCSSCCR3},
+       {"trcssccr4", A64SysReg_TRCSSCCR4},
+       {"trcssccr5", A64SysReg_TRCSSCCR5},
+       {"trcssccr6", A64SysReg_TRCSSCCR6},
+       {"trcssccr7", A64SysReg_TRCSSCCR7},
+       {"trcsscsr0", A64SysReg_TRCSSCSR0},
+       {"trcsscsr1", A64SysReg_TRCSSCSR1},
+       {"trcsscsr2", A64SysReg_TRCSSCSR2},
+       {"trcsscsr3", A64SysReg_TRCSSCSR3},
+       {"trcsscsr4", A64SysReg_TRCSSCSR4},
+       {"trcsscsr5", A64SysReg_TRCSSCSR5},
+       {"trcsscsr6", A64SysReg_TRCSSCSR6},
+       {"trcsscsr7", A64SysReg_TRCSSCSR7},
+       {"trcsspcicr0", A64SysReg_TRCSSPCICR0},
+       {"trcsspcicr1", A64SysReg_TRCSSPCICR1},
+       {"trcsspcicr2", A64SysReg_TRCSSPCICR2},
+       {"trcsspcicr3", A64SysReg_TRCSSPCICR3},
+       {"trcsspcicr4", A64SysReg_TRCSSPCICR4},
+       {"trcsspcicr5", A64SysReg_TRCSSPCICR5},
+       {"trcsspcicr6", A64SysReg_TRCSSPCICR6},
+       {"trcsspcicr7", A64SysReg_TRCSSPCICR7},
+       {"trcpdcr", A64SysReg_TRCPDCR},
+       {"trcacvr0", A64SysReg_TRCACVR0},
+       {"trcacvr1", A64SysReg_TRCACVR1},
+       {"trcacvr2", A64SysReg_TRCACVR2},
+       {"trcacvr3", A64SysReg_TRCACVR3},
+       {"trcacvr4", A64SysReg_TRCACVR4},
+       {"trcacvr5", A64SysReg_TRCACVR5},
+       {"trcacvr6", A64SysReg_TRCACVR6},
+       {"trcacvr7", A64SysReg_TRCACVR7},
+       {"trcacvr8", A64SysReg_TRCACVR8},
+       {"trcacvr9", A64SysReg_TRCACVR9},
+       {"trcacvr10", A64SysReg_TRCACVR10},
+       {"trcacvr11", A64SysReg_TRCACVR11},
+       {"trcacvr12", A64SysReg_TRCACVR12},
+       {"trcacvr13", A64SysReg_TRCACVR13},
+       {"trcacvr14", A64SysReg_TRCACVR14},
+       {"trcacvr15", A64SysReg_TRCACVR15},
+       {"trcacatr0", A64SysReg_TRCACATR0},
+       {"trcacatr1", A64SysReg_TRCACATR1},
+       {"trcacatr2", A64SysReg_TRCACATR2},
+       {"trcacatr3", A64SysReg_TRCACATR3},
+       {"trcacatr4", A64SysReg_TRCACATR4},
+       {"trcacatr5", A64SysReg_TRCACATR5},
+       {"trcacatr6", A64SysReg_TRCACATR6},
+       {"trcacatr7", A64SysReg_TRCACATR7},
+       {"trcacatr8", A64SysReg_TRCACATR8},
+       {"trcacatr9", A64SysReg_TRCACATR9},
+       {"trcacatr10", A64SysReg_TRCACATR10},
+       {"trcacatr11", A64SysReg_TRCACATR11},
+       {"trcacatr12", A64SysReg_TRCACATR12},
+       {"trcacatr13", A64SysReg_TRCACATR13},
+       {"trcacatr14", A64SysReg_TRCACATR14},
+       {"trcacatr15", A64SysReg_TRCACATR15},
+       {"trcdvcvr0", A64SysReg_TRCDVCVR0},
+       {"trcdvcvr1", A64SysReg_TRCDVCVR1},
+       {"trcdvcvr2", A64SysReg_TRCDVCVR2},
+       {"trcdvcvr3", A64SysReg_TRCDVCVR3},
+       {"trcdvcvr4", A64SysReg_TRCDVCVR4},
+       {"trcdvcvr5", A64SysReg_TRCDVCVR5},
+       {"trcdvcvr6", A64SysReg_TRCDVCVR6},
+       {"trcdvcvr7", A64SysReg_TRCDVCVR7},
+       {"trcdvcmr0", A64SysReg_TRCDVCMR0},
+       {"trcdvcmr1", A64SysReg_TRCDVCMR1},
+       {"trcdvcmr2", A64SysReg_TRCDVCMR2},
+       {"trcdvcmr3", A64SysReg_TRCDVCMR3},
+       {"trcdvcmr4", A64SysReg_TRCDVCMR4},
+       {"trcdvcmr5", A64SysReg_TRCDVCMR5},
+       {"trcdvcmr6", A64SysReg_TRCDVCMR6},
+       {"trcdvcmr7", A64SysReg_TRCDVCMR7},
+       {"trccidcvr0", A64SysReg_TRCCIDCVR0},
+       {"trccidcvr1", A64SysReg_TRCCIDCVR1},
+       {"trccidcvr2", A64SysReg_TRCCIDCVR2},
+       {"trccidcvr3", A64SysReg_TRCCIDCVR3},
+       {"trccidcvr4", A64SysReg_TRCCIDCVR4},
+       {"trccidcvr5", A64SysReg_TRCCIDCVR5},
+       {"trccidcvr6", A64SysReg_TRCCIDCVR6},
+       {"trccidcvr7", A64SysReg_TRCCIDCVR7},
+       {"trcvmidcvr0", A64SysReg_TRCVMIDCVR0},
+       {"trcvmidcvr1", A64SysReg_TRCVMIDCVR1},
+       {"trcvmidcvr2", A64SysReg_TRCVMIDCVR2},
+       {"trcvmidcvr3", A64SysReg_TRCVMIDCVR3},
+       {"trcvmidcvr4", A64SysReg_TRCVMIDCVR4},
+       {"trcvmidcvr5", A64SysReg_TRCVMIDCVR5},
+       {"trcvmidcvr6", A64SysReg_TRCVMIDCVR6},
+       {"trcvmidcvr7", A64SysReg_TRCVMIDCVR7},
+       {"trccidcctlr0", A64SysReg_TRCCIDCCTLR0},
+       {"trccidcctlr1", A64SysReg_TRCCIDCCTLR1},
+       {"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0},
+       {"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1},
+       {"trcitctrl", A64SysReg_TRCITCTRL},
+       {"trcclaimset", A64SysReg_TRCCLAIMSET},
+       {"trcclaimclr", A64SysReg_TRCCLAIMCLR},
+
+       // GICv3 registers
+       {"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1},
+       {"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1},
+       {"icc_pmr_el1", A64SysReg_ICC_PMR_EL1},
+       {"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1},
+       {"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3},
+       {"icc_sre_el1", A64SysReg_ICC_SRE_EL1},
+       {"icc_sre_el2", A64SysReg_ICC_SRE_EL2},
+       {"icc_sre_el3", A64SysReg_ICC_SRE_EL3},
+       {"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1},
+       {"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1},
+       {"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3},
+       {"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1},
+       {"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1},
+       {"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1},
+       {"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1},
+       {"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1},
+       {"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1},
+       {"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1},
+       {"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1},
+       {"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1},
+       {"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2},
+       {"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2},
+       {"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2},
+       {"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2},
+       {"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2},
+       {"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2},
+       {"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2},
+       {"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2},
+       {"ich_hcr_el2", A64SysReg_ICH_HCR_EL2},
+       {"ich_misr_el2", A64SysReg_ICH_MISR_EL2},
+       {"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2},
+       {"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2},
+       {"ich_lr0_el2", A64SysReg_ICH_LR0_EL2},
+       {"ich_lr1_el2", A64SysReg_ICH_LR1_EL2},
+       {"ich_lr2_el2", A64SysReg_ICH_LR2_EL2},
+       {"ich_lr3_el2", A64SysReg_ICH_LR3_EL2},
+       {"ich_lr4_el2", A64SysReg_ICH_LR4_EL2},
+       {"ich_lr5_el2", A64SysReg_ICH_LR5_EL2},
+       {"ich_lr6_el2", A64SysReg_ICH_LR6_EL2},
+       {"ich_lr7_el2", A64SysReg_ICH_LR7_EL2},
+       {"ich_lr8_el2", A64SysReg_ICH_LR8_EL2},
+       {"ich_lr9_el2", A64SysReg_ICH_LR9_EL2},
+       {"ich_lr10_el2", A64SysReg_ICH_LR10_EL2},
+       {"ich_lr11_el2", A64SysReg_ICH_LR11_EL2},
+       {"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
+       {"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
+       {"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
+       {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2}
+};
+
+// result must be a big enough buffer: 128 bytes is more than enough
+void SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
+{
+       unsigned i;
+       for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
+               if (SysRegPairs[i].Value == Bits) {
+                       *Valid = true;
+                       strcpy(result, SysRegPairs[i].Name);
+                       return;
+               }
+       }
+
+       for (i = 0; i < S->NumInstPairs; ++i) {
+               if (S->InstPairs[i].Value == Bits) {
+                       *Valid = true;
+                       strcpy(result, S->InstPairs[i].Name);
+                       return;
+               }
+       }
+
+       uint32_t Op0 = (Bits >> 14) & 0x3;
+       uint32_t Op1 = (Bits >> 11) & 0x7;
+       uint32_t CRn = (Bits >> 7) & 0xf;
+       uint32_t CRm = (Bits >> 3) & 0xf;
+       uint32_t Op2 = Bits & 0x7;
+
+       // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
+       // name.
+       if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
+               *Valid = false;
+               return;
+       }
+
+       //assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
+
+       *Valid = true;
+
+       char *Op1S, *CRnS, *CRmS, *Op2S;
+       Op1S = utostr(Op1, false);
+       CRnS = utostr(CRn, false);
+       CRmS = utostr(CRm, false);
+       Op2S = utostr(Op2, false);
+
+       //printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
+       int dummy = sprintf(result, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
+       (void)dummy;
+
+       free(Op1S);
+       free(CRnS);
+       free(CRmS);
+       free(Op2S);
+}
+
+static NamedImmMapper_Mapping TLBIPairs[] = {
+       {"ipas2e1is", A64TLBI_IPAS2E1IS},
+       {"ipas2le1is", A64TLBI_IPAS2LE1IS},
+       {"vmalle1is", A64TLBI_VMALLE1IS},
+       {"alle2is", A64TLBI_ALLE2IS},
+       {"alle3is", A64TLBI_ALLE3IS},
+       {"vae1is", A64TLBI_VAE1IS},
+       {"vae2is", A64TLBI_VAE2IS},
+       {"vae3is", A64TLBI_VAE3IS},
+       {"aside1is", A64TLBI_ASIDE1IS},
+       {"vaae1is", A64TLBI_VAAE1IS},
+       {"alle1is", A64TLBI_ALLE1IS},
+       {"vale1is", A64TLBI_VALE1IS},
+       {"vale2is", A64TLBI_VALE2IS},
+       {"vale3is", A64TLBI_VALE3IS},
+       {"vmalls12e1is", A64TLBI_VMALLS12E1IS},
+       {"vaale1is", A64TLBI_VAALE1IS},
+       {"ipas2e1", A64TLBI_IPAS2E1},
+       {"ipas2le1", A64TLBI_IPAS2LE1},
+       {"vmalle1", A64TLBI_VMALLE1},
+       {"alle2", A64TLBI_ALLE2},
+       {"alle3", A64TLBI_ALLE3},
+       {"vae1", A64TLBI_VAE1},
+       {"vae2", A64TLBI_VAE2},
+       {"vae3", A64TLBI_VAE3},
+       {"aside1", A64TLBI_ASIDE1},
+       {"vaae1", A64TLBI_VAAE1},
+       {"alle1", A64TLBI_ALLE1},
+       {"vale1", A64TLBI_VALE1},
+       {"vale2", A64TLBI_VALE2},
+       {"vale3", A64TLBI_VALE3},
+       {"vmalls12e1", A64TLBI_VMALLS12E1},
+       {"vaale1", A64TLBI_VAALE1}
+};
+
+NamedImmMapper AArch64_TLBIMapper = {
+       .Pairs = TLBIPairs,
+       .NumPairs = ARR_SIZE(TLBIPairs),
+       .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping ATPairs[] = {
+       {"s1e1r", A64AT_S1E1R},
+       {"s1e2r", A64AT_S1E2R},
+       {"s1e3r", A64AT_S1E3R},
+       {"s1e1w", A64AT_S1E1W},
+       {"s1e2w", A64AT_S1E2W},
+       {"s1e3w", A64AT_S1E3W},
+       {"s1e0r", A64AT_S1E0R},
+       {"s1e0w", A64AT_S1E0W},
+       {"s12e1r", A64AT_S12E1R},
+       {"s12e1w", A64AT_S12E1W},
+       {"s12e0r", A64AT_S12E0R},
+       {"s12e0w", A64AT_S12E0W},
+};
+
+NamedImmMapper AArch64_ATMapper = {
+       .Pairs = ATPairs,
+       .NumPairs = ARR_SIZE(ATPairs),
+       .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping DBarrierPairs[] = {
+       {"oshld", A64DB_OSHLD},
+       {"oshst", A64DB_OSHST},
+       {"osh", A64DB_OSH},
+       {"nshld", A64DB_NSHLD},
+       {"nshst", A64DB_NSHST},
+       {"nsh", A64DB_NSH},
+       {"ishld", A64DB_ISHLD},
+       {"ishst", A64DB_ISHST},
+       {"ish", A64DB_ISH},
+       {"ld", A64DB_LD},
+       {"st", A64DB_ST},
+       {"sy", A64DB_SY}
+};
+
+NamedImmMapper AArch64_DBarrierMapper = {
+       .Pairs = DBarrierPairs,
+       .NumPairs = ARR_SIZE(DBarrierPairs),
+       .TooBigImm = 16,
+};
+
+static NamedImmMapper_Mapping DCPairs[] = {
+       {"zva", A64DC_ZVA},
+       {"ivac", A64DC_IVAC},
+       {"isw", A64DC_ISW},
+       {"cvac", A64DC_CVAC},
+       {"csw", A64DC_CSW},
+       {"cvau", A64DC_CVAU},
+       {"civac", A64DC_CIVAC},
+       {"cisw", A64DC_CISW}
+};
+
+NamedImmMapper AArch64_DCMapper = {
+       .Pairs = DCPairs,
+       .NumPairs = ARR_SIZE(DCPairs),
+       .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping ICPairs[] = {
+       {"ialluis",  A64IC_IALLUIS},
+       {"iallu", A64IC_IALLU},
+       {"ivau", A64IC_IVAU}
+};
+
+NamedImmMapper AArch64_ICMapper = {
+       .Pairs = ICPairs,
+       .NumPairs = ARR_SIZE(ICPairs),
+       .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping ISBPairs[] = {
+       {"sy",  A64DB_SY},
+};
+
+NamedImmMapper AArch64_ISBMapper = {
+       .Pairs = ISBPairs,
+       .NumPairs = ARR_SIZE(ISBPairs),
+       .TooBigImm = 16,
+};
+
+static NamedImmMapper_Mapping PRFMPairs[] = {
+       {"pldl1keep", A64PRFM_PLDL1KEEP},
+       {"pldl1strm", A64PRFM_PLDL1STRM},
+       {"pldl2keep", A64PRFM_PLDL2KEEP},
+       {"pldl2strm", A64PRFM_PLDL2STRM},
+       {"pldl3keep", A64PRFM_PLDL3KEEP},
+       {"pldl3strm", A64PRFM_PLDL3STRM},
+       {"plil1keep", A64PRFM_PLIL1KEEP},
+       {"plil1strm", A64PRFM_PLIL1STRM},
+       {"plil2keep", A64PRFM_PLIL2KEEP},
+       {"plil2strm", A64PRFM_PLIL2STRM},
+       {"plil3keep", A64PRFM_PLIL3KEEP},
+       {"plil3strm", A64PRFM_PLIL3STRM},
+       {"pstl1keep", A64PRFM_PSTL1KEEP},
+       {"pstl1strm", A64PRFM_PSTL1STRM},
+       {"pstl2keep", A64PRFM_PSTL2KEEP},
+       {"pstl2strm", A64PRFM_PSTL2STRM},
+       {"pstl3keep", A64PRFM_PSTL3KEEP},
+       {"pstl3strm", A64PRFM_PSTL3STRM}
+};
+
+NamedImmMapper AArch64_PRFMMapper = {
+       .Pairs = PRFMPairs,
+       .NumPairs = ARR_SIZE(PRFMPairs),
+       .TooBigImm = 32,
+};
+
+static NamedImmMapper_Mapping PStatePairs[] = {
+       {"spsel", A64PState_SPSel},
+       {"daifset", A64PState_DAIFSet},
+       {"daifclr", A64PState_DAIFClr}
+};
+
+NamedImmMapper AArch64_PStateMapper = {
+       .Pairs = PStatePairs,
+       .NumPairs = ARR_SIZE(PStatePairs),
+       .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping MRSPairs[] = {
+       {"mdccsr_el0", A64SysReg_MDCCSR_EL0},
+       {"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
+       {"mdrar_el1", A64SysReg_MDRAR_EL1},
+       {"oslsr_el1", A64SysReg_OSLSR_EL1},
+       {"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1},
+       {"pmceid0_el0", A64SysReg_PMCEID0_EL0},
+       {"pmceid1_el0", A64SysReg_PMCEID1_EL0},
+       {"midr_el1", A64SysReg_MIDR_EL1},
+       {"ccsidr_el1", A64SysReg_CCSIDR_EL1},
+       {"clidr_el1", A64SysReg_CLIDR_EL1},
+       {"ctr_el0", A64SysReg_CTR_EL0},
+       {"mpidr_el1", A64SysReg_MPIDR_EL1},
+       {"revidr_el1", A64SysReg_REVIDR_EL1},
+       {"aidr_el1", A64SysReg_AIDR_EL1},
+       {"dczid_el0", A64SysReg_DCZID_EL0},
+       {"id_pfr0_el1", A64SysReg_ID_PFR0_EL1},
+       {"id_pfr1_el1", A64SysReg_ID_PFR1_EL1},
+       {"id_dfr0_el1", A64SysReg_ID_DFR0_EL1},
+       {"id_afr0_el1", A64SysReg_ID_AFR0_EL1},
+       {"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1},
+       {"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
+       {"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
+       {"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
+       {"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
+       {"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
+       {"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
+       {"id_isar3_el1", A64SysReg_ID_ISAR3_EL1},
+       {"id_isar4_el1", A64SysReg_ID_ISAR4_EL1},
+       {"id_isar5_el1", A64SysReg_ID_ISAR5_EL1},
+       {"id_aa64pfr0_el1", A64SysReg_ID_AA64PFR0_EL1},
+       {"id_aa64pfr1_el1", A64SysReg_ID_AA64PFR1_EL1},
+       {"id_aa64dfr0_el1", A64SysReg_ID_AA64DFR0_EL1},
+       {"id_aa64dfr1_el1", A64SysReg_ID_AA64DFR1_EL1},
+       {"id_aa64afr0_el1", A64SysReg_ID_AA64AFR0_EL1},
+       {"id_aa64afr1_el1", A64SysReg_ID_AA64AFR1_EL1},
+       {"id_aa64isar0_el1", A64SysReg_ID_AA64ISAR0_EL1},
+       {"id_aa64isar1_el1", A64SysReg_ID_AA64ISAR1_EL1},
+       {"id_aa64mmfr0_el1", A64SysReg_ID_AA64MMFR0_EL1},
+       {"id_aa64mmfr1_el1", A64SysReg_ID_AA64MMFR1_EL1},
+       {"mvfr0_el1", A64SysReg_MVFR0_EL1},
+       {"mvfr1_el1", A64SysReg_MVFR1_EL1},
+       {"mvfr2_el1", A64SysReg_MVFR2_EL1},
+       {"rvbar_el1", A64SysReg_RVBAR_EL1},
+       {"rvbar_el2", A64SysReg_RVBAR_EL2},
+       {"rvbar_el3", A64SysReg_RVBAR_EL3},
+       {"isr_el1", A64SysReg_ISR_EL1},
+       {"cntpct_el0", A64SysReg_CNTPCT_EL0},
+       {"cntvct_el0", A64SysReg_CNTVCT_EL0},
+
+       // Trace registers
+       {"trcstatr", A64SysReg_TRCSTATR},
+       {"trcidr8", A64SysReg_TRCIDR8},
+       {"trcidr9", A64SysReg_TRCIDR9},
+       {"trcidr10", A64SysReg_TRCIDR10},
+       {"trcidr11", A64SysReg_TRCIDR11},
+       {"trcidr12", A64SysReg_TRCIDR12},
+       {"trcidr13", A64SysReg_TRCIDR13},
+       {"trcidr0", A64SysReg_TRCIDR0},
+       {"trcidr1", A64SysReg_TRCIDR1},
+       {"trcidr2", A64SysReg_TRCIDR2},
+       {"trcidr3", A64SysReg_TRCIDR3},
+       {"trcidr4", A64SysReg_TRCIDR4},
+       {"trcidr5", A64SysReg_TRCIDR5},
+       {"trcidr6", A64SysReg_TRCIDR6},
+       {"trcidr7", A64SysReg_TRCIDR7},
+       {"trcoslsr", A64SysReg_TRCOSLSR},
+       {"trcpdsr", A64SysReg_TRCPDSR},
+       {"trcdevaff0", A64SysReg_TRCDEVAFF0},
+       {"trcdevaff1", A64SysReg_TRCDEVAFF1},
+       {"trclsr", A64SysReg_TRCLSR},
+       {"trcauthstatus", A64SysReg_TRCAUTHSTATUS},
+       {"trcdevarch", A64SysReg_TRCDEVARCH},
+       {"trcdevid", A64SysReg_TRCDEVID},
+       {"trcdevtype", A64SysReg_TRCDEVTYPE},
+       {"trcpidr4", A64SysReg_TRCPIDR4},
+       {"trcpidr5", A64SysReg_TRCPIDR5},
+       {"trcpidr6", A64SysReg_TRCPIDR6},
+       {"trcpidr7", A64SysReg_TRCPIDR7},
+       {"trcpidr0", A64SysReg_TRCPIDR0},
+       {"trcpidr1", A64SysReg_TRCPIDR1},
+       {"trcpidr2", A64SysReg_TRCPIDR2},
+       {"trcpidr3", A64SysReg_TRCPIDR3},
+       {"trccidr0", A64SysReg_TRCCIDR0},
+       {"trccidr1", A64SysReg_TRCCIDR1},
+       {"trccidr2", A64SysReg_TRCCIDR2},
+       {"trccidr3", A64SysReg_TRCCIDR3},
+
+       // GICv3 registers
+       {"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1},
+       {"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1},
+       {"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1},
+       {"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1},
+       {"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
+       {"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
+       {"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
+       {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2}
+};
+
+SysRegMapper AArch64_MRSMapper = {
+       .InstPairs = MRSPairs,
+       .NumInstPairs = ARR_SIZE(MRSPairs),
+};
+
+static NamedImmMapper_Mapping MSRPairs[] = {
+       {"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
+       {"oslar_el1", A64SysReg_OSLAR_EL1},
+       {"pmswinc_el0", A64SysReg_PMSWINC_EL0},
+
+       // Trace registers
+       {"trcoslar", A64SysReg_TRCOSLAR},
+       {"trclar", A64SysReg_TRCLAR},
+
+       // GICv3 registers
+       {"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1},
+       {"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1},
+       {"icc_dir_el1", A64SysReg_ICC_DIR_EL1},
+       {"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1},
+       {"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1},
+       {"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
+};
+
+SysRegMapper AArch64_MSRMapper = {
+       .InstPairs = MSRPairs,
+       .NumInstPairs = ARR_SIZE(MSRPairs),
+};
+
+// Encoding of the immediate for logical (immediate) instructions:
+//
+// | N | imms   | immr   | size | R            | S            |
+// |---+--------+--------+------+--------------+--------------|
+// | 1 | ssssss | rrrrrr |   64 | UInt(rrrrrr) | UInt(ssssss) |
+// | 0 | 0sssss | xrrrrr |   32 | UInt(rrrrr)  | UInt(sssss)  |
+// | 0 | 10ssss | xxrrrr |   16 | UInt(rrrr)   | UInt(ssss)   |
+// | 0 | 110sss | xxxrrr |    8 | UInt(rrr)    | UInt(sss)    |
+// | 0 | 1110ss | xxxxrr |    4 | UInt(rr)     | UInt(ss)     |
+// | 0 | 11110s | xxxxxr |    2 | UInt(r)      | UInt(s)      |
+// | 0 | 11111x | -      |      | UNALLOCATED  |              |
+//
+// Columns 'R', 'S' and 'size' specify a "bitmask immediate" of size bits in
+// which the lower S+1 bits are ones and the remaining bits are zero, then
+// rotated right by R bits, which is then replicated across the datapath.
+//
+// + Values of 'N', 'imms' and 'immr' which do not match the above table are
+//   RESERVED.
+// + If all 's' bits in the imms field are set then the instruction is
+//   RESERVED.
+// + The 'x' bits in the 'immr' field are IGNORED.
+bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm)
+{
+       uint32_t N = Bits >> 12;
+       uint32_t ImmR = (Bits >> 6) & 0x3f;
+       uint32_t ImmS = Bits & 0x3f;
+
+       // N=1 encodes a 64-bit replication and is invalid for the 32-bit
+       // instructions.
+       if (RegWidth == 32 && N != 0) return false;
+
+       int Width = 0;
+       if (N == 1)
+               Width = 64;
+       else if ((ImmS & 0x20) == 0)
+               Width = 32;
+       else if ((ImmS & 0x10) == 0)
+               Width = 16;
+       else if ((ImmS & 0x08) == 0)
+               Width = 8;
+       else if ((ImmS & 0x04) == 0)
+               Width = 4;
+       else if ((ImmS & 0x02) == 0)
+               Width = 2;
+       else {
+               // ImmS  is 0b11111x: UNALLOCATED
+               return false;
+       }
+
+       int Num1s = (ImmS & (Width - 1)) + 1;
+
+       // All encodings which would map to -1 (signed) are RESERVED.
+       if (Num1s == Width) return false;
+
+       int Rotation = (ImmR & (Width - 1));
+       uint64_t Mask = (1ULL << Num1s) - 1;
+       uint64_t WidthMask = Width == 64 ? -1 : (1ULL << Width) - 1;
+       if (Rotation != 0 && Rotation != 64)
+               Mask = (Mask >> Rotation)
+                       | ((Mask << (Width - Rotation)) & WidthMask);
+
+       *Imm = Mask;
+       unsigned i;
+       for (i = 1; i < RegWidth / Width; ++i) {
+               Mask <<= Width;
+               *Imm |= Mask;
+       }
+
+       return true;
+}
+
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
new file mode 100644 (file)
index 0000000..a2a0313
--- /dev/null
@@ -0,0 +1,903 @@
+//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the AArch64 target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_AARCH64_BASEINFO_H
+#define CS_LLVM_AARCH64_BASEINFO_H
+
+#include <ctype.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+
+/// Instances of this class can perform bidirectional mapping from random
+/// identifier strings to operand encodings. For example "MSR" takes a named
+/// system-register which must be encoded somehow and decoded for printing. This
+/// central location means that the information for those transformations is not
+/// duplicated and remains in sync.
+///
+/// FIXME: currently the algorithm is a completely unoptimised linear
+/// search. Obviously this could be improved, but we would probably want to work
+/// out just how often these instructions are emitted before working on it. It
+/// might even be optimal to just reorder the tables for the common instructions
+/// rather than changing the algorithm.
+typedef struct NamedImmMapper_Mapping {
+       char *Name;
+       uint32_t Value;
+} NamedImmMapper_Mapping;
+
+typedef struct NamedImmMapper {
+       NamedImmMapper_Mapping *Pairs;
+       size_t NumPairs;
+       uint32_t TooBigImm;
+} NamedImmMapper;
+
+typedef struct SysRegMapper {
+       NamedImmMapper_Mapping *SysRegPairs;
+       NamedImmMapper_Mapping *InstPairs;
+       size_t NumInstPairs;
+} SysRegMapper;
+
+extern SysRegMapper AArch64_MSRMapper;
+extern SysRegMapper AArch64_MRSMapper;
+
+extern NamedImmMapper AArch64_DBarrierMapper;
+extern NamedImmMapper AArch64_ATMapper;
+extern NamedImmMapper AArch64_DCMapper;
+extern NamedImmMapper AArch64_ICMapper;
+extern NamedImmMapper AArch64_ISBMapper;
+extern NamedImmMapper AArch64_PRFMMapper;
+extern NamedImmMapper AArch64_PStateMapper;
+extern NamedImmMapper AArch64_TLBIMapper;
+
+// // Enums corresponding to AArch64 condition codes
+// The CondCodes constants map directly to the 4-bit encoding of the
+// condition field for predicated instructions.
+typedef enum A64CC_CondCodes {   // Meaning (integer)          Meaning (floating-point)
+       A64CC_EQ = 0,        // Equal                      Equal
+       A64CC_NE,            // Not equal                  Not equal, or unordered
+       A64CC_HS,            // Unsigned higher or same    >, ==, or unordered
+       A64CC_LO,            // Unsigned lower or same     Less than
+       A64CC_MI,            // Minus, negative            Less than
+       A64CC_PL,            // Plus, positive or zero     >, ==, or unordered
+       A64CC_VS,            // Overflow                   Unordered
+       A64CC_VC,            // No overflow                Ordered
+       A64CC_HI,            // Unsigned higher            Greater than, or unordered
+       A64CC_LS,            // Unsigned lower or same     Less than or equal
+       A64CC_GE,            // Greater than or equal      Greater than or equal
+       A64CC_LT,            // Less than                  Less than, or unordered
+       A64CC_GT,            // Signed greater than        Greater than
+       A64CC_LE,            // Signed less than or equal  <, ==, or unordered
+       A64CC_AL,            // Always (unconditional)     Always (unconditional)
+       A64CC_NV,             // Always (unconditional)     Always (unconditional)
+       // Note the NV exists purely to disassemble 0b1111. Execution
+       // is "always".
+       A64CC_Invalid
+} A64CC_CondCodes;
+
+inline static const char *A64CondCodeToString(A64CC_CondCodes CC)
+{
+       switch (CC) {
+               default: return 0;      // never reach
+               case A64CC_EQ:  return "eq";
+               case A64CC_NE:  return "ne";
+               case A64CC_HS:  return "hs";
+               case A64CC_LO:  return "lo";
+               case A64CC_MI:  return "mi";
+               case A64CC_PL:  return "pl";
+               case A64CC_VS:  return "vs";
+               case A64CC_VC:  return "vc";
+               case A64CC_HI:  return "hi";
+               case A64CC_LS:  return "ls";
+               case A64CC_GE:  return "ge";
+               case A64CC_LT:  return "lt";
+               case A64CC_GT:  return "gt";
+               case A64CC_LE:  return "le";
+               case A64CC_AL:  return "al";
+               case A64CC_NV:  return "nv";
+       }
+}
+
+enum {
+       A64AT_Invalid = -1,    // Op0 Op1  CRn   CRm   Op2
+       A64AT_S1E1R = 0x43c0,  // 01  000  0111  1000  000
+       A64AT_S1E2R = 0x63c0,  // 01  100  0111  1000  000
+       A64AT_S1E3R = 0x73c0,  // 01  110  0111  1000  000
+       A64AT_S1E1W = 0x43c1,  // 01  000  0111  1000  001
+       A64AT_S1E2W = 0x63c1,  // 01  100  0111  1000  001
+       A64AT_S1E3W = 0x73c1,  // 01  110  0111  1000  001
+       A64AT_S1E0R = 0x43c2,  // 01  000  0111  1000  010
+       A64AT_S1E0W = 0x43c3,  // 01  000  0111  1000  011
+       A64AT_S12E1R = 0x63c4, // 01  100  0111  1000  100
+       A64AT_S12E1W = 0x63c5, // 01  100  0111  1000  101
+       A64AT_S12E0R = 0x63c6, // 01  100  0111  1000  110
+       A64AT_S12E0W = 0x63c7  // 01  100  0111  1000  111
+};
+
+enum DBValues {
+       A64DB_Invalid = -1,
+       A64DB_OSHLD = 0x1,
+       A64DB_OSHST = 0x2,
+       A64DB_OSH =   0x3,
+       A64DB_NSHLD = 0x5,
+       A64DB_NSHST = 0x6,
+       A64DB_NSH =   0x7,
+       A64DB_ISHLD = 0x9,
+       A64DB_ISHST = 0xa,
+       A64DB_ISH =   0xb,
+       A64DB_LD =    0xd,
+       A64DB_ST =    0xe,
+       A64DB_SY =    0xf
+};
+
+enum DCValues {
+       A64DC_Invalid = -1,   // Op1  CRn   CRm   Op2
+       A64DC_ZVA   = 0x5ba1, // 01  011  0111  0100  001
+       A64DC_IVAC  = 0x43b1, // 01  000  0111  0110  001
+       A64DC_ISW   = 0x43b2, // 01  000  0111  0110  010
+       A64DC_CVAC  = 0x5bd1, // 01  011  0111  1010  001
+       A64DC_CSW   = 0x43d2, // 01  000  0111  1010  010
+       A64DC_CVAU  = 0x5bd9, // 01  011  0111  1011  001
+       A64DC_CIVAC = 0x5bf1, // 01  011  0111  1110  001
+       A64DC_CISW  = 0x43f2  // 01  000  0111  1110  010
+};
+
+enum ICValues {
+       A64IC_Invalid = -1,     // Op1  CRn   CRm   Op2
+       A64IC_IALLUIS = 0x0388, // 000  0111  0001  000
+       A64IC_IALLU = 0x03a8,   // 000  0111  0101  000
+       A64IC_IVAU = 0x1ba9     // 011  0111  0101  001
+};
+
+enum ISBValues {
+       A64ISB_Invalid = -1,
+       A64ISB_SY = 0xf
+};
+
+enum PRFMValues {
+       A64PRFM_Invalid = -1,
+       A64PRFM_PLDL1KEEP = 0x00,
+       A64PRFM_PLDL1STRM = 0x01,
+       A64PRFM_PLDL2KEEP = 0x02,
+       A64PRFM_PLDL2STRM = 0x03,
+       A64PRFM_PLDL3KEEP = 0x04,
+       A64PRFM_PLDL3STRM = 0x05,
+       A64PRFM_PLIL1KEEP = 0x08,
+       A64PRFM_PLIL1STRM = 0x09,
+       A64PRFM_PLIL2KEEP = 0x0a,
+       A64PRFM_PLIL2STRM = 0x0b,
+       A64PRFM_PLIL3KEEP = 0x0c,
+       A64PRFM_PLIL3STRM = 0x0d,
+       A64PRFM_PSTL1KEEP = 0x10,
+       A64PRFM_PSTL1STRM = 0x11,
+       A64PRFM_PSTL2KEEP = 0x12,
+       A64PRFM_PSTL2STRM = 0x13,
+       A64PRFM_PSTL3KEEP = 0x14,
+       A64PRFM_PSTL3STRM = 0x15
+};
+
+enum PStateValues {
+       A64PState_Invalid = -1,
+       A64PState_SPSel = 0x05,
+       A64PState_DAIFSet = 0x1e,
+       A64PState_DAIFClr = 0x1f
+};
+
+typedef enum A64SE_ShiftExtSpecifiers {
+       A64SE_Invalid = -1,
+       A64SE_LSL,
+       A64SE_MSL,
+       A64SE_LSR,
+       A64SE_ASR,
+       A64SE_ROR,
+
+       A64SE_UXTB,
+       A64SE_UXTH,
+       A64SE_UXTW,
+       A64SE_UXTX,
+
+       A64SE_SXTB,
+       A64SE_SXTH,
+       A64SE_SXTW,
+       A64SE_SXTX
+} A64SE_ShiftExtSpecifiers;
+
+typedef enum A64Layout_VectorLayout {
+       A64Layout_Invalid = -1,
+       A64Layout_VL_8B,
+       A64Layout_VL_4H,
+       A64Layout_VL_2S,
+       A64Layout_VL_1D,
+
+       A64Layout_VL_16B,
+       A64Layout_VL_8H,
+       A64Layout_VL_4S,
+       A64Layout_VL_2D,
+
+       // Bare layout for the 128-bit vector
+       // (only show ".b", ".h", ".s", ".d" without vector number)
+       A64Layout_VL_B,
+       A64Layout_VL_H,
+       A64Layout_VL_S,
+       A64Layout_VL_D
+} A64Layout_VectorLayout;
+
+inline static const char *
+A64VectorLayoutToString(A64Layout_VectorLayout Layout)
+{
+       switch (Layout) {
+               case A64Layout_VL_8B:  return ".8b";
+               case A64Layout_VL_4H:  return ".4h";
+               case A64Layout_VL_2S:  return ".2s";
+               case A64Layout_VL_1D:  return ".1d";
+               case A64Layout_VL_16B:  return ".16b";
+               case A64Layout_VL_8H:  return ".8h";
+               case A64Layout_VL_4S:  return ".4s";
+               case A64Layout_VL_2D:  return ".2d";
+               case A64Layout_VL_B:  return ".b";
+               case A64Layout_VL_H:  return ".h";
+               case A64Layout_VL_S:  return ".s";
+               case A64Layout_VL_D:  return ".d";
+               default: return NULL;   // never reach
+       }
+}
+
+enum SysRegROValues {
+       A64SysReg_MDCCSR_EL0        = 0x9808, // 10  011  0000  0001  000
+       A64SysReg_DBGDTRRX_EL0      = 0x9828, // 10  011  0000  0101  000
+       A64SysReg_MDRAR_EL1         = 0x8080, // 10  000  0001  0000  000
+       A64SysReg_OSLSR_EL1         = 0x808c, // 10  000  0001  0001  100
+       A64SysReg_DBGAUTHSTATUS_EL1 = 0x83f6, // 10  000  0111  1110  110
+       A64SysReg_PMCEID0_EL0       = 0xdce6, // 11  011  1001  1100  110
+       A64SysReg_PMCEID1_EL0       = 0xdce7, // 11  011  1001  1100  111
+       A64SysReg_MIDR_EL1          = 0xc000, // 11  000  0000  0000  000
+       A64SysReg_CCSIDR_EL1        = 0xc800, // 11  001  0000  0000  000
+       A64SysReg_CLIDR_EL1         = 0xc801, // 11  001  0000  0000  001
+       A64SysReg_CTR_EL0           = 0xd801, // 11  011  0000  0000  001
+       A64SysReg_MPIDR_EL1         = 0xc005, // 11  000  0000  0000  101
+       A64SysReg_REVIDR_EL1        = 0xc006, // 11  000  0000  0000  110
+       A64SysReg_AIDR_EL1          = 0xc807, // 11  001  0000  0000  111
+       A64SysReg_DCZID_EL0         = 0xd807, // 11  011  0000  0000  111
+       A64SysReg_ID_PFR0_EL1       = 0xc008, // 11  000  0000  0001  000
+       A64SysReg_ID_PFR1_EL1       = 0xc009, // 11  000  0000  0001  001
+       A64SysReg_ID_DFR0_EL1       = 0xc00a, // 11  000  0000  0001  010
+       A64SysReg_ID_AFR0_EL1       = 0xc00b, // 11  000  0000  0001  011
+       A64SysReg_ID_MMFR0_EL1      = 0xc00c, // 11  000  0000  0001  100
+       A64SysReg_ID_MMFR1_EL1      = 0xc00d, // 11  000  0000  0001  101
+       A64SysReg_ID_MMFR2_EL1      = 0xc00e, // 11  000  0000  0001  110
+       A64SysReg_ID_MMFR3_EL1      = 0xc00f, // 11  000  0000  0001  111
+       A64SysReg_ID_ISAR0_EL1      = 0xc010, // 11  000  0000  0010  000
+       A64SysReg_ID_ISAR1_EL1      = 0xc011, // 11  000  0000  0010  001
+       A64SysReg_ID_ISAR2_EL1      = 0xc012, // 11  000  0000  0010  010
+       A64SysReg_ID_ISAR3_EL1      = 0xc013, // 11  000  0000  0010  011
+       A64SysReg_ID_ISAR4_EL1      = 0xc014, // 11  000  0000  0010  100
+       A64SysReg_ID_ISAR5_EL1      = 0xc015, // 11  000  0000  0010  101
+       A64SysReg_ID_AA64PFR0_EL1   = 0xc020, // 11  000  0000  0100  000
+       A64SysReg_ID_AA64PFR1_EL1   = 0xc021, // 11  000  0000  0100  001
+       A64SysReg_ID_AA64DFR0_EL1   = 0xc028, // 11  000  0000  0101  000
+       A64SysReg_ID_AA64DFR1_EL1   = 0xc029, // 11  000  0000  0101  001
+       A64SysReg_ID_AA64AFR0_EL1   = 0xc02c, // 11  000  0000  0101  100
+       A64SysReg_ID_AA64AFR1_EL1   = 0xc02d, // 11  000  0000  0101  101
+       A64SysReg_ID_AA64ISAR0_EL1  = 0xc030, // 11  000  0000  0110  000
+       A64SysReg_ID_AA64ISAR1_EL1  = 0xc031, // 11  000  0000  0110  001
+       A64SysReg_ID_AA64MMFR0_EL1  = 0xc038, // 11  000  0000  0111  000
+       A64SysReg_ID_AA64MMFR1_EL1  = 0xc039, // 11  000  0000  0111  001
+       A64SysReg_MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
+       A64SysReg_MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
+       A64SysReg_MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
+       A64SysReg_RVBAR_EL1         = 0xc601, // 11  000  1100  0000  001
+       A64SysReg_RVBAR_EL2         = 0xe601, // 11  100  1100  0000  001
+       A64SysReg_RVBAR_EL3         = 0xf601, // 11  110  1100  0000  001
+       A64SysReg_ISR_EL1           = 0xc608, // 11  000  1100  0001  000
+       A64SysReg_CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
+       A64SysReg_CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010
+
+       // Trace registers
+       A64SysReg_TRCSTATR          = 0x8818, // 10  001  0000  0011  000
+       A64SysReg_TRCIDR8           = 0x8806, // 10  001  0000  0000  110
+       A64SysReg_TRCIDR9           = 0x880e, // 10  001  0000  0001  110
+       A64SysReg_TRCIDR10          = 0x8816, // 10  001  0000  0010  110
+       A64SysReg_TRCIDR11          = 0x881e, // 10  001  0000  0011  110
+       A64SysReg_TRCIDR12          = 0x8826, // 10  001  0000  0100  110
+       A64SysReg_TRCIDR13          = 0x882e, // 10  001  0000  0101  110
+       A64SysReg_TRCIDR0           = 0x8847, // 10  001  0000  1000  111
+       A64SysReg_TRCIDR1           = 0x884f, // 10  001  0000  1001  111
+       A64SysReg_TRCIDR2           = 0x8857, // 10  001  0000  1010  111
+       A64SysReg_TRCIDR3           = 0x885f, // 10  001  0000  1011  111
+       A64SysReg_TRCIDR4           = 0x8867, // 10  001  0000  1100  111
+       A64SysReg_TRCIDR5           = 0x886f, // 10  001  0000  1101  111
+       A64SysReg_TRCIDR6           = 0x8877, // 10  001  0000  1110  111
+       A64SysReg_TRCIDR7           = 0x887f, // 10  001  0000  1111  111
+       A64SysReg_TRCOSLSR          = 0x888c, // 10  001  0001  0001  100
+       A64SysReg_TRCPDSR           = 0x88ac, // 10  001  0001  0101  100
+       A64SysReg_TRCDEVAFF0        = 0x8bd6, // 10  001  0111  1010  110
+       A64SysReg_TRCDEVAFF1        = 0x8bde, // 10  001  0111  1011  110
+       A64SysReg_TRCLSR            = 0x8bee, // 10  001  0111  1101  110
+       A64SysReg_TRCAUTHSTATUS     = 0x8bf6, // 10  001  0111  1110  110
+       A64SysReg_TRCDEVARCH        = 0x8bfe, // 10  001  0111  1111  110
+       A64SysReg_TRCDEVID          = 0x8b97, // 10  001  0111  0010  111
+       A64SysReg_TRCDEVTYPE        = 0x8b9f, // 10  001  0111  0011  111
+       A64SysReg_TRCPIDR4          = 0x8ba7, // 10  001  0111  0100  111
+       A64SysReg_TRCPIDR5          = 0x8baf, // 10  001  0111  0101  111
+       A64SysReg_TRCPIDR6          = 0x8bb7, // 10  001  0111  0110  111
+       A64SysReg_TRCPIDR7          = 0x8bbf, // 10  001  0111  0111  111
+       A64SysReg_TRCPIDR0          = 0x8bc7, // 10  001  0111  1000  111
+       A64SysReg_TRCPIDR1          = 0x8bcf, // 10  001  0111  1001  111
+       A64SysReg_TRCPIDR2          = 0x8bd7, // 10  001  0111  1010  111
+       A64SysReg_TRCPIDR3          = 0x8bdf, // 10  001  0111  1011  111
+       A64SysReg_TRCCIDR0          = 0x8be7, // 10  001  0111  1100  111
+       A64SysReg_TRCCIDR1          = 0x8bef, // 10  001  0111  1101  111
+       A64SysReg_TRCCIDR2          = 0x8bf7, // 10  001  0111  1110  111
+       A64SysReg_TRCCIDR3          = 0x8bff, // 10  001  0111  1111  111
+
+       // GICv3 registers
+       A64SysReg_ICC_IAR1_EL1      = 0xc660, // 11  000  1100  1100  000
+       A64SysReg_ICC_IAR0_EL1      = 0xc640, // 11  000  1100  1000  000
+       A64SysReg_ICC_HPPIR1_EL1    = 0xc662, // 11  000  1100  1100  010
+       A64SysReg_ICC_HPPIR0_EL1    = 0xc642, // 11  000  1100  1000  010
+       A64SysReg_ICC_RPR_EL1       = 0xc65b, // 11  000  1100  1011  011
+       A64SysReg_ICH_VTR_EL2       = 0xe659, // 11  100  1100  1011  001
+       A64SysReg_ICH_EISR_EL2      = 0xe65b, // 11  100  1100  1011  011
+       A64SysReg_ICH_ELSR_EL2      = 0xe65d  // 11  100  1100  1011  101
+};
+
+enum SysRegWOValues {
+       A64SysReg_DBGDTRTX_EL0      = 0x9828, // 10  011  0000  0101  000
+       A64SysReg_OSLAR_EL1         = 0x8084, // 10  000  0001  0000  100
+       A64SysReg_PMSWINC_EL0       = 0xdce4,  // 11  011  1001  1100  100
+
+       // Trace Registers
+       A64SysReg_TRCOSLAR          = 0x8884, // 10  001  0001  0000  100
+       A64SysReg_TRCLAR            = 0x8be6, // 10  001  0111  1100  110
+
+       // GICv3 registers
+       A64SysReg_ICC_EOIR1_EL1     = 0xc661, // 11  000  1100  1100  001
+       A64SysReg_ICC_EOIR0_EL1     = 0xc641, // 11  000  1100  1000  001
+       A64SysReg_ICC_DIR_EL1       = 0xc659, // 11  000  1100  1011  001
+       A64SysReg_ICC_SGI1R_EL1     = 0xc65d, // 11  000  1100  1011  101
+       A64SysReg_ICC_ASGI1R_EL1    = 0xc65e, // 11  000  1100  1011  110
+       A64SysReg_ICC_SGI0R_EL1     = 0xc65f  // 11  000  1100  1011  111
+};
+
+enum SysRegValues {
+       A64SysReg_Invalid = -1,               // Op0 Op1  CRn   CRm   Op2
+       A64SysReg_OSDTRRX_EL1       = 0x8002, // 10  000  0000  0000  010
+       A64SysReg_OSDTRTX_EL1       = 0x801a, // 10  000  0000  0011  010
+       A64SysReg_TEECR32_EL1       = 0x9000, // 10  010  0000  0000  000
+       A64SysReg_MDCCINT_EL1       = 0x8010, // 10  000  0000  0010  000
+       A64SysReg_MDSCR_EL1         = 0x8012, // 10  000  0000  0010  010
+       A64SysReg_DBGDTR_EL0        = 0x9820, // 10  011  0000  0100  000
+       A64SysReg_OSECCR_EL1        = 0x8032, // 10  000  0000  0110  010
+       A64SysReg_DBGVCR32_EL2      = 0xa038, // 10  100  0000  0111  000
+       A64SysReg_DBGBVR0_EL1       = 0x8004, // 10  000  0000  0000  100
+       A64SysReg_DBGBVR1_EL1       = 0x800c, // 10  000  0000  0001  100
+       A64SysReg_DBGBVR2_EL1       = 0x8014, // 10  000  0000  0010  100
+       A64SysReg_DBGBVR3_EL1       = 0x801c, // 10  000  0000  0011  100
+       A64SysReg_DBGBVR4_EL1       = 0x8024, // 10  000  0000  0100  100
+       A64SysReg_DBGBVR5_EL1       = 0x802c, // 10  000  0000  0101  100
+       A64SysReg_DBGBVR6_EL1       = 0x8034, // 10  000  0000  0110  100
+       A64SysReg_DBGBVR7_EL1       = 0x803c, // 10  000  0000  0111  100
+       A64SysReg_DBGBVR8_EL1       = 0x8044, // 10  000  0000  1000  100
+       A64SysReg_DBGBVR9_EL1       = 0x804c, // 10  000  0000  1001  100
+       A64SysReg_DBGBVR10_EL1      = 0x8054, // 10  000  0000  1010  100
+       A64SysReg_DBGBVR11_EL1      = 0x805c, // 10  000  0000  1011  100
+       A64SysReg_DBGBVR12_EL1      = 0x8064, // 10  000  0000  1100  100
+       A64SysReg_DBGBVR13_EL1      = 0x806c, // 10  000  0000  1101  100
+       A64SysReg_DBGBVR14_EL1      = 0x8074, // 10  000  0000  1110  100
+       A64SysReg_DBGBVR15_EL1      = 0x807c, // 10  000  0000  1111  100
+       A64SysReg_DBGBCR0_EL1       = 0x8005, // 10  000  0000  0000  101
+       A64SysReg_DBGBCR1_EL1       = 0x800d, // 10  000  0000  0001  101
+       A64SysReg_DBGBCR2_EL1       = 0x8015, // 10  000  0000  0010  101
+       A64SysReg_DBGBCR3_EL1       = 0x801d, // 10  000  0000  0011  101
+       A64SysReg_DBGBCR4_EL1       = 0x8025, // 10  000  0000  0100  101
+       A64SysReg_DBGBCR5_EL1       = 0x802d, // 10  000  0000  0101  101
+       A64SysReg_DBGBCR6_EL1       = 0x8035, // 10  000  0000  0110  101
+       A64SysReg_DBGBCR7_EL1       = 0x803d, // 10  000  0000  0111  101
+       A64SysReg_DBGBCR8_EL1       = 0x8045, // 10  000  0000  1000  101
+       A64SysReg_DBGBCR9_EL1       = 0x804d, // 10  000  0000  1001  101
+       A64SysReg_DBGBCR10_EL1      = 0x8055, // 10  000  0000  1010  101
+       A64SysReg_DBGBCR11_EL1      = 0x805d, // 10  000  0000  1011  101
+       A64SysReg_DBGBCR12_EL1      = 0x8065, // 10  000  0000  1100  101
+       A64SysReg_DBGBCR13_EL1      = 0x806d, // 10  000  0000  1101  101
+       A64SysReg_DBGBCR14_EL1      = 0x8075, // 10  000  0000  1110  101
+       A64SysReg_DBGBCR15_EL1      = 0x807d, // 10  000  0000  1111  101
+       A64SysReg_DBGWVR0_EL1       = 0x8006, // 10  000  0000  0000  110
+       A64SysReg_DBGWVR1_EL1       = 0x800e, // 10  000  0000  0001  110
+       A64SysReg_DBGWVR2_EL1       = 0x8016, // 10  000  0000  0010  110
+       A64SysReg_DBGWVR3_EL1       = 0x801e, // 10  000  0000  0011  110
+       A64SysReg_DBGWVR4_EL1       = 0x8026, // 10  000  0000  0100  110
+       A64SysReg_DBGWVR5_EL1       = 0x802e, // 10  000  0000  0101  110
+       A64SysReg_DBGWVR6_EL1       = 0x8036, // 10  000  0000  0110  110
+       A64SysReg_DBGWVR7_EL1       = 0x803e, // 10  000  0000  0111  110
+       A64SysReg_DBGWVR8_EL1       = 0x8046, // 10  000  0000  1000  110
+       A64SysReg_DBGWVR9_EL1       = 0x804e, // 10  000  0000  1001  110
+       A64SysReg_DBGWVR10_EL1      = 0x8056, // 10  000  0000  1010  110
+       A64SysReg_DBGWVR11_EL1      = 0x805e, // 10  000  0000  1011  110
+       A64SysReg_DBGWVR12_EL1      = 0x8066, // 10  000  0000  1100  110
+       A64SysReg_DBGWVR13_EL1      = 0x806e, // 10  000  0000  1101  110
+       A64SysReg_DBGWVR14_EL1      = 0x8076, // 10  000  0000  1110  110
+       A64SysReg_DBGWVR15_EL1      = 0x807e, // 10  000  0000  1111  110
+       A64SysReg_DBGWCR0_EL1       = 0x8007, // 10  000  0000  0000  111
+       A64SysReg_DBGWCR1_EL1       = 0x800f, // 10  000  0000  0001  111
+       A64SysReg_DBGWCR2_EL1       = 0x8017, // 10  000  0000  0010  111
+       A64SysReg_DBGWCR3_EL1       = 0x801f, // 10  000  0000  0011  111
+       A64SysReg_DBGWCR4_EL1       = 0x8027, // 10  000  0000  0100  111
+       A64SysReg_DBGWCR5_EL1       = 0x802f, // 10  000  0000  0101  111
+       A64SysReg_DBGWCR6_EL1       = 0x8037, // 10  000  0000  0110  111
+       A64SysReg_DBGWCR7_EL1       = 0x803f, // 10  000  0000  0111  111
+       A64SysReg_DBGWCR8_EL1       = 0x8047, // 10  000  0000  1000  111
+       A64SysReg_DBGWCR9_EL1       = 0x804f, // 10  000  0000  1001  111
+       A64SysReg_DBGWCR10_EL1      = 0x8057, // 10  000  0000  1010  111
+       A64SysReg_DBGWCR11_EL1      = 0x805f, // 10  000  0000  1011  111
+       A64SysReg_DBGWCR12_EL1      = 0x8067, // 10  000  0000  1100  111
+       A64SysReg_DBGWCR13_EL1      = 0x806f, // 10  000  0000  1101  111
+       A64SysReg_DBGWCR14_EL1      = 0x8077, // 10  000  0000  1110  111
+       A64SysReg_DBGWCR15_EL1      = 0x807f, // 10  000  0000  1111  111
+       A64SysReg_TEEHBR32_EL1      = 0x9080, // 10  010  0001  0000  000
+       A64SysReg_OSDLR_EL1         = 0x809c, // 10  000  0001  0011  100
+       A64SysReg_DBGPRCR_EL1       = 0x80a4, // 10  000  0001  0100  100
+       A64SysReg_DBGCLAIMSET_EL1   = 0x83c6, // 10  000  0111  1000  110
+       A64SysReg_DBGCLAIMCLR_EL1   = 0x83ce, // 10  000  0111  1001  110
+       A64SysReg_CSSELR_EL1        = 0xd000, // 11  010  0000  0000  000
+       A64SysReg_VPIDR_EL2         = 0xe000, // 11  100  0000  0000  000
+       A64SysReg_VMPIDR_EL2        = 0xe005, // 11  100  0000  0000  101
+       A64SysReg_CPACR_EL1         = 0xc082, // 11  000  0001  0000  010
+       A64SysReg_SCTLR_EL1         = 0xc080, // 11  000  0001  0000  000
+       A64SysReg_SCTLR_EL2         = 0xe080, // 11  100  0001  0000  000
+       A64SysReg_SCTLR_EL3         = 0xf080, // 11  110  0001  0000  000
+       A64SysReg_ACTLR_EL1         = 0xc081, // 11  000  0001  0000  001
+       A64SysReg_ACTLR_EL2         = 0xe081, // 11  100  0001  0000  001
+       A64SysReg_ACTLR_EL3         = 0xf081, // 11  110  0001  0000  001
+       A64SysReg_HCR_EL2           = 0xe088, // 11  100  0001  0001  000
+       A64SysReg_SCR_EL3           = 0xf088, // 11  110  0001  0001  000
+       A64SysReg_MDCR_EL2          = 0xe089, // 11  100  0001  0001  001
+       A64SysReg_SDER32_EL3        = 0xf089, // 11  110  0001  0001  001
+       A64SysReg_CPTR_EL2          = 0xe08a, // 11  100  0001  0001  010
+       A64SysReg_CPTR_EL3          = 0xf08a, // 11  110  0001  0001  010
+       A64SysReg_HSTR_EL2          = 0xe08b, // 11  100  0001  0001  011
+       A64SysReg_HACR_EL2          = 0xe08f, // 11  100  0001  0001  111
+       A64SysReg_MDCR_EL3          = 0xf099, // 11  110  0001  0011  001
+       A64SysReg_TTBR0_EL1         = 0xc100, // 11  000  0010  0000  000
+       A64SysReg_TTBR0_EL2         = 0xe100, // 11  100  0010  0000  000
+       A64SysReg_TTBR0_EL3         = 0xf100, // 11  110  0010  0000  000
+       A64SysReg_TTBR1_EL1         = 0xc101, // 11  000  0010  0000  001
+       A64SysReg_TCR_EL1           = 0xc102, // 11  000  0010  0000  010
+       A64SysReg_TCR_EL2           = 0xe102, // 11  100  0010  0000  010
+       A64SysReg_TCR_EL3           = 0xf102, // 11  110  0010  0000  010
+       A64SysReg_VTTBR_EL2         = 0xe108, // 11  100  0010  0001  000
+       A64SysReg_VTCR_EL2          = 0xe10a, // 11  100  0010  0001  010
+       A64SysReg_DACR32_EL2        = 0xe180, // 11  100  0011  0000  000
+       A64SysReg_SPSR_EL1          = 0xc200, // 11  000  0100  0000  000
+       A64SysReg_SPSR_EL2          = 0xe200, // 11  100  0100  0000  000
+       A64SysReg_SPSR_EL3          = 0xf200, // 11  110  0100  0000  000
+       A64SysReg_ELR_EL1           = 0xc201, // 11  000  0100  0000  001
+       A64SysReg_ELR_EL2           = 0xe201, // 11  100  0100  0000  001
+       A64SysReg_ELR_EL3           = 0xf201, // 11  110  0100  0000  001
+       A64SysReg_SP_EL0            = 0xc208, // 11  000  0100  0001  000
+       A64SysReg_SP_EL1            = 0xe208, // 11  100  0100  0001  000
+       A64SysReg_SP_EL2            = 0xf208, // 11  110  0100  0001  000
+       A64SysReg_SPSel             = 0xc210, // 11  000  0100  0010  000
+       A64SysReg_NZCV              = 0xda10, // 11  011  0100  0010  000
+       A64SysReg_DAIF              = 0xda11, // 11  011  0100  0010  001
+       A64SysReg_CurrentEL         = 0xc212, // 11  000  0100  0010  010
+       A64SysReg_SPSR_irq          = 0xe218, // 11  100  0100  0011  000
+       A64SysReg_SPSR_abt          = 0xe219, // 11  100  0100  0011  001
+       A64SysReg_SPSR_und          = 0xe21a, // 11  100  0100  0011  010
+       A64SysReg_SPSR_fiq          = 0xe21b, // 11  100  0100  0011  011
+       A64SysReg_FPCR              = 0xda20, // 11  011  0100  0100  000
+       A64SysReg_FPSR              = 0xda21, // 11  011  0100  0100  001
+       A64SysReg_DSPSR_EL0         = 0xda28, // 11  011  0100  0101  000
+       A64SysReg_DLR_EL0           = 0xda29, // 11  011  0100  0101  001
+       A64SysReg_IFSR32_EL2        = 0xe281, // 11  100  0101  0000  001
+       A64SysReg_AFSR0_EL1         = 0xc288, // 11  000  0101  0001  000
+       A64SysReg_AFSR0_EL2         = 0xe288, // 11  100  0101  0001  000
+       A64SysReg_AFSR0_EL3         = 0xf288, // 11  110  0101  0001  000
+       A64SysReg_AFSR1_EL1         = 0xc289, // 11  000  0101  0001  001
+       A64SysReg_AFSR1_EL2         = 0xe289, // 11  100  0101  0001  001
+       A64SysReg_AFSR1_EL3         = 0xf289, // 11  110  0101  0001  001
+       A64SysReg_ESR_EL1           = 0xc290, // 11  000  0101  0010  000
+       A64SysReg_ESR_EL2           = 0xe290, // 11  100  0101  0010  000
+       A64SysReg_ESR_EL3           = 0xf290, // 11  110  0101  0010  000
+       A64SysReg_FPEXC32_EL2       = 0xe298, // 11  100  0101  0011  000
+       A64SysReg_FAR_EL1           = 0xc300, // 11  000  0110  0000  000
+       A64SysReg_FAR_EL2           = 0xe300, // 11  100  0110  0000  000
+       A64SysReg_FAR_EL3           = 0xf300, // 11  110  0110  0000  000
+       A64SysReg_HPFAR_EL2         = 0xe304, // 11  100  0110  0000  100
+       A64SysReg_PAR_EL1           = 0xc3a0, // 11  000  0111  0100  000
+       A64SysReg_PMCR_EL0          = 0xdce0, // 11  011  1001  1100  000
+       A64SysReg_PMCNTENSET_EL0    = 0xdce1, // 11  011  1001  1100  001
+       A64SysReg_PMCNTENCLR_EL0    = 0xdce2, // 11  011  1001  1100  010
+       A64SysReg_PMOVSCLR_EL0      = 0xdce3, // 11  011  1001  1100  011
+       A64SysReg_PMSELR_EL0        = 0xdce5, // 11  011  1001  1100  101
+       A64SysReg_PMCCNTR_EL0       = 0xdce8, // 11  011  1001  1101  000
+       A64SysReg_PMXEVTYPER_EL0    = 0xdce9, // 11  011  1001  1101  001
+       A64SysReg_PMXEVCNTR_EL0     = 0xdcea, // 11  011  1001  1101  010
+       A64SysReg_PMUSERENR_EL0     = 0xdcf0, // 11  011  1001  1110  000
+       A64SysReg_PMINTENSET_EL1    = 0xc4f1, // 11  000  1001  1110  001
+       A64SysReg_PMINTENCLR_EL1    = 0xc4f2, // 11  000  1001  1110  010
+       A64SysReg_PMOVSSET_EL0      = 0xdcf3, // 11  011  1001  1110  011
+       A64SysReg_MAIR_EL1          = 0xc510, // 11  000  1010  0010  000
+       A64SysReg_MAIR_EL2          = 0xe510, // 11  100  1010  0010  000
+       A64SysReg_MAIR_EL3          = 0xf510, // 11  110  1010  0010  000
+       A64SysReg_AMAIR_EL1         = 0xc518, // 11  000  1010  0011  000
+       A64SysReg_AMAIR_EL2         = 0xe518, // 11  100  1010  0011  000
+       A64SysReg_AMAIR_EL3         = 0xf518, // 11  110  1010  0011  000
+       A64SysReg_VBAR_EL1          = 0xc600, // 11  000  1100  0000  000
+       A64SysReg_VBAR_EL2          = 0xe600, // 11  100  1100  0000  000
+       A64SysReg_VBAR_EL3          = 0xf600, // 11  110  1100  0000  000
+       A64SysReg_RMR_EL1           = 0xc602, // 11  000  1100  0000  010
+       A64SysReg_RMR_EL2           = 0xe602, // 11  100  1100  0000  010
+       A64SysReg_RMR_EL3           = 0xf602, // 11  110  1100  0000  010
+       A64SysReg_CONTEXTIDR_EL1    = 0xc681, // 11  000  1101  0000  001
+       A64SysReg_TPIDR_EL0         = 0xde82, // 11  011  1101  0000  010
+       A64SysReg_TPIDR_EL2         = 0xe682, // 11  100  1101  0000  010
+       A64SysReg_TPIDR_EL3         = 0xf682, // 11  110  1101  0000  010
+       A64SysReg_TPIDRRO_EL0       = 0xde83, // 11  011  1101  0000  011
+       A64SysReg_TPIDR_EL1         = 0xc684, // 11  000  1101  0000  100
+       A64SysReg_CNTFRQ_EL0        = 0xdf00, // 11  011  1110  0000  000
+       A64SysReg_CNTVOFF_EL2       = 0xe703, // 11  100  1110  0000  011
+       A64SysReg_CNTKCTL_EL1       = 0xc708, // 11  000  1110  0001  000
+       A64SysReg_CNTHCTL_EL2       = 0xe708, // 11  100  1110  0001  000
+       A64SysReg_CNTP_TVAL_EL0     = 0xdf10, // 11  011  1110  0010  000
+       A64SysReg_CNTHP_TVAL_EL2    = 0xe710, // 11  100  1110  0010  000
+       A64SysReg_CNTPS_TVAL_EL1    = 0xff10, // 11  111  1110  0010  000
+       A64SysReg_CNTP_CTL_EL0      = 0xdf11, // 11  011  1110  0010  001
+       A64SysReg_CNTHP_CTL_EL2     = 0xe711, // 11  100  1110  0010  001
+       A64SysReg_CNTPS_CTL_EL1     = 0xff11, // 11  111  1110  0010  001
+       A64SysReg_CNTP_CVAL_EL0     = 0xdf12, // 11  011  1110  0010  010
+       A64SysReg_CNTHP_CVAL_EL2    = 0xe712, // 11  100  1110  0010  010
+       A64SysReg_CNTPS_CVAL_EL1    = 0xff12, // 11  111  1110  0010  010
+       A64SysReg_CNTV_TVAL_EL0     = 0xdf18, // 11  011  1110  0011  000
+       A64SysReg_CNTV_CTL_EL0      = 0xdf19, // 11  011  1110  0011  001
+       A64SysReg_CNTV_CVAL_EL0     = 0xdf1a, // 11  011  1110  0011  010
+       A64SysReg_PMEVCNTR0_EL0     = 0xdf40, // 11  011  1110  1000  000
+       A64SysReg_PMEVCNTR1_EL0     = 0xdf41, // 11  011  1110  1000  001
+       A64SysReg_PMEVCNTR2_EL0     = 0xdf42, // 11  011  1110  1000  010
+       A64SysReg_PMEVCNTR3_EL0     = 0xdf43, // 11  011  1110  1000  011
+       A64SysReg_PMEVCNTR4_EL0     = 0xdf44, // 11  011  1110  1000  100
+       A64SysReg_PMEVCNTR5_EL0     = 0xdf45, // 11  011  1110  1000  101
+       A64SysReg_PMEVCNTR6_EL0     = 0xdf46, // 11  011  1110  1000  110
+       A64SysReg_PMEVCNTR7_EL0     = 0xdf47, // 11  011  1110  1000  111
+       A64SysReg_PMEVCNTR8_EL0     = 0xdf48, // 11  011  1110  1001  000
+       A64SysReg_PMEVCNTR9_EL0     = 0xdf49, // 11  011  1110  1001  001
+       A64SysReg_PMEVCNTR10_EL0    = 0xdf4a, // 11  011  1110  1001  010
+       A64SysReg_PMEVCNTR11_EL0    = 0xdf4b, // 11  011  1110  1001  011
+       A64SysReg_PMEVCNTR12_EL0    = 0xdf4c, // 11  011  1110  1001  100
+       A64SysReg_PMEVCNTR13_EL0    = 0xdf4d, // 11  011  1110  1001  101
+       A64SysReg_PMEVCNTR14_EL0    = 0xdf4e, // 11  011  1110  1001  110
+       A64SysReg_PMEVCNTR15_EL0    = 0xdf4f, // 11  011  1110  1001  111
+       A64SysReg_PMEVCNTR16_EL0    = 0xdf50, // 11  011  1110  1010  000
+       A64SysReg_PMEVCNTR17_EL0    = 0xdf51, // 11  011  1110  1010  001
+       A64SysReg_PMEVCNTR18_EL0    = 0xdf52, // 11  011  1110  1010  010
+       A64SysReg_PMEVCNTR19_EL0    = 0xdf53, // 11  011  1110  1010  011
+       A64SysReg_PMEVCNTR20_EL0    = 0xdf54, // 11  011  1110  1010  100
+       A64SysReg_PMEVCNTR21_EL0    = 0xdf55, // 11  011  1110  1010  101
+       A64SysReg_PMEVCNTR22_EL0    = 0xdf56, // 11  011  1110  1010  110
+       A64SysReg_PMEVCNTR23_EL0    = 0xdf57, // 11  011  1110  1010  111
+       A64SysReg_PMEVCNTR24_EL0    = 0xdf58, // 11  011  1110  1011  000
+       A64SysReg_PMEVCNTR25_EL0    = 0xdf59, // 11  011  1110  1011  001
+       A64SysReg_PMEVCNTR26_EL0    = 0xdf5a, // 11  011  1110  1011  010
+       A64SysReg_PMEVCNTR27_EL0    = 0xdf5b, // 11  011  1110  1011  011
+       A64SysReg_PMEVCNTR28_EL0    = 0xdf5c, // 11  011  1110  1011  100
+       A64SysReg_PMEVCNTR29_EL0    = 0xdf5d, // 11  011  1110  1011  101
+       A64SysReg_PMEVCNTR30_EL0    = 0xdf5e, // 11  011  1110  1011  110
+       A64SysReg_PMCCFILTR_EL0     = 0xdf7f, // 11  011  1110  1111  111
+       A64SysReg_PMEVTYPER0_EL0    = 0xdf60, // 11  011  1110  1100  000
+       A64SysReg_PMEVTYPER1_EL0    = 0xdf61, // 11  011  1110  1100  001
+       A64SysReg_PMEVTYPER2_EL0    = 0xdf62, // 11  011  1110  1100  010
+       A64SysReg_PMEVTYPER3_EL0    = 0xdf63, // 11  011  1110  1100  011
+       A64SysReg_PMEVTYPER4_EL0    = 0xdf64, // 11  011  1110  1100  100
+       A64SysReg_PMEVTYPER5_EL0    = 0xdf65, // 11  011  1110  1100  101
+       A64SysReg_PMEVTYPER6_EL0    = 0xdf66, // 11  011  1110  1100  110
+       A64SysReg_PMEVTYPER7_EL0    = 0xdf67, // 11  011  1110  1100  111
+       A64SysReg_PMEVTYPER8_EL0    = 0xdf68, // 11  011  1110  1101  000
+       A64SysReg_PMEVTYPER9_EL0    = 0xdf69, // 11  011  1110  1101  001
+       A64SysReg_PMEVTYPER10_EL0   = 0xdf6a, // 11  011  1110  1101  010
+       A64SysReg_PMEVTYPER11_EL0   = 0xdf6b, // 11  011  1110  1101  011
+       A64SysReg_PMEVTYPER12_EL0   = 0xdf6c, // 11  011  1110  1101  100
+       A64SysReg_PMEVTYPER13_EL0   = 0xdf6d, // 11  011  1110  1101  101
+       A64SysReg_PMEVTYPER14_EL0   = 0xdf6e, // 11  011  1110  1101  110
+       A64SysReg_PMEVTYPER15_EL0   = 0xdf6f, // 11  011  1110  1101  111
+       A64SysReg_PMEVTYPER16_EL0   = 0xdf70, // 11  011  1110  1110  000
+       A64SysReg_PMEVTYPER17_EL0   = 0xdf71, // 11  011  1110  1110  001
+       A64SysReg_PMEVTYPER18_EL0   = 0xdf72, // 11  011  1110  1110  010
+       A64SysReg_PMEVTYPER19_EL0   = 0xdf73, // 11  011  1110  1110  011
+       A64SysReg_PMEVTYPER20_EL0   = 0xdf74, // 11  011  1110  1110  100
+       A64SysReg_PMEVTYPER21_EL0   = 0xdf75, // 11  011  1110  1110  101
+       A64SysReg_PMEVTYPER22_EL0   = 0xdf76, // 11  011  1110  1110  110
+       A64SysReg_PMEVTYPER23_EL0   = 0xdf77, // 11  011  1110  1110  111
+       A64SysReg_PMEVTYPER24_EL0   = 0xdf78, // 11  011  1110  1111  000
+       A64SysReg_PMEVTYPER25_EL0   = 0xdf79, // 11  011  1110  1111  001
+       A64SysReg_PMEVTYPER26_EL0   = 0xdf7a, // 11  011  1110  1111  010
+       A64SysReg_PMEVTYPER27_EL0   = 0xdf7b, // 11  011  1110  1111  011
+       A64SysReg_PMEVTYPER28_EL0   = 0xdf7c, // 11  011  1110  1111  100
+       A64SysReg_PMEVTYPER29_EL0   = 0xdf7d, // 11  011  1110  1111  101
+       A64SysReg_PMEVTYPER30_EL0   = 0xdf7e, // 11  011  1110  1111  110
+
+       // Trace registers
+       A64SysReg_TRCPRGCTLR        = 0x8808, // 10  001  0000  0001  000
+       A64SysReg_TRCPROCSELR       = 0x8810, // 10  001  0000  0010  000
+       A64SysReg_TRCCONFIGR        = 0x8820, // 10  001  0000  0100  000
+       A64SysReg_TRCAUXCTLR        = 0x8830, // 10  001  0000  0110  000
+       A64SysReg_TRCEVENTCTL0R     = 0x8840, // 10  001  0000  1000  000
+       A64SysReg_TRCEVENTCTL1R     = 0x8848, // 10  001  0000  1001  000
+       A64SysReg_TRCSTALLCTLR      = 0x8858, // 10  001  0000  1011  000
+       A64SysReg_TRCTSCTLR         = 0x8860, // 10  001  0000  1100  000
+       A64SysReg_TRCSYNCPR         = 0x8868, // 10  001  0000  1101  000
+       A64SysReg_TRCCCCTLR         = 0x8870, // 10  001  0000  1110  000
+       A64SysReg_TRCBBCTLR         = 0x8878, // 10  001  0000  1111  000
+       A64SysReg_TRCTRACEIDR       = 0x8801, // 10  001  0000  0000  001
+       A64SysReg_TRCQCTLR          = 0x8809, // 10  001  0000  0001  001
+       A64SysReg_TRCVICTLR         = 0x8802, // 10  001  0000  0000  010
+       A64SysReg_TRCVIIECTLR       = 0x880a, // 10  001  0000  0001  010
+       A64SysReg_TRCVISSCTLR       = 0x8812, // 10  001  0000  0010  010
+       A64SysReg_TRCVIPCSSCTLR     = 0x881a, // 10  001  0000  0011  010
+       A64SysReg_TRCVDCTLR         = 0x8842, // 10  001  0000  1000  010
+       A64SysReg_TRCVDSACCTLR      = 0x884a, // 10  001  0000  1001  010
+       A64SysReg_TRCVDARCCTLR      = 0x8852, // 10  001  0000  1010  010
+       A64SysReg_TRCSEQEVR0        = 0x8804, // 10  001  0000  0000  100
+       A64SysReg_TRCSEQEVR1        = 0x880c, // 10  001  0000  0001  100
+       A64SysReg_TRCSEQEVR2        = 0x8814, // 10  001  0000  0010  100
+       A64SysReg_TRCSEQRSTEVR      = 0x8834, // 10  001  0000  0110  100
+       A64SysReg_TRCSEQSTR         = 0x883c, // 10  001  0000  0111  100
+       A64SysReg_TRCEXTINSELR      = 0x8844, // 10  001  0000  1000  100
+       A64SysReg_TRCCNTRLDVR0      = 0x8805, // 10  001  0000  0000  101
+       A64SysReg_TRCCNTRLDVR1      = 0x880d, // 10  001  0000  0001  101
+       A64SysReg_TRCCNTRLDVR2      = 0x8815, // 10  001  0000  0010  101
+       A64SysReg_TRCCNTRLDVR3      = 0x881d, // 10  001  0000  0011  101
+       A64SysReg_TRCCNTCTLR0       = 0x8825, // 10  001  0000  0100  101
+       A64SysReg_TRCCNTCTLR1       = 0x882d, // 10  001  0000  0101  101
+       A64SysReg_TRCCNTCTLR2       = 0x8835, // 10  001  0000  0110  101
+       A64SysReg_TRCCNTCTLR3       = 0x883d, // 10  001  0000  0111  101
+       A64SysReg_TRCCNTVR0         = 0x8845, // 10  001  0000  1000  101
+       A64SysReg_TRCCNTVR1         = 0x884d, // 10  001  0000  1001  101
+       A64SysReg_TRCCNTVR2         = 0x8855, // 10  001  0000  1010  101
+       A64SysReg_TRCCNTVR3         = 0x885d, // 10  001  0000  1011  101
+       A64SysReg_TRCIMSPEC0        = 0x8807, // 10  001  0000  0000  111
+       A64SysReg_TRCIMSPEC1        = 0x880f, // 10  001  0000  0001  111
+       A64SysReg_TRCIMSPEC2        = 0x8817, // 10  001  0000  0010  111
+       A64SysReg_TRCIMSPEC3        = 0x881f, // 10  001  0000  0011  111
+       A64SysReg_TRCIMSPEC4        = 0x8827, // 10  001  0000  0100  111
+       A64SysReg_TRCIMSPEC5        = 0x882f, // 10  001  0000  0101  111
+       A64SysReg_TRCIMSPEC6        = 0x8837, // 10  001  0000  0110  111
+       A64SysReg_TRCIMSPEC7        = 0x883f, // 10  001  0000  0111  111
+       A64SysReg_TRCRSCTLR2        = 0x8890, // 10  001  0001  0010  000
+       A64SysReg_TRCRSCTLR3        = 0x8898, // 10  001  0001  0011  000
+       A64SysReg_TRCRSCTLR4        = 0x88a0, // 10  001  0001  0100  000
+       A64SysReg_TRCRSCTLR5        = 0x88a8, // 10  001  0001  0101  000
+       A64SysReg_TRCRSCTLR6        = 0x88b0, // 10  001  0001  0110  000
+       A64SysReg_TRCRSCTLR7        = 0x88b8, // 10  001  0001  0111  000
+       A64SysReg_TRCRSCTLR8        = 0x88c0, // 10  001  0001  1000  000
+       A64SysReg_TRCRSCTLR9        = 0x88c8, // 10  001  0001  1001  000
+       A64SysReg_TRCRSCTLR10       = 0x88d0, // 10  001  0001  1010  000
+       A64SysReg_TRCRSCTLR11       = 0x88d8, // 10  001  0001  1011  000
+       A64SysReg_TRCRSCTLR12       = 0x88e0, // 10  001  0001  1100  000
+       A64SysReg_TRCRSCTLR13       = 0x88e8, // 10  001  0001  1101  000
+       A64SysReg_TRCRSCTLR14       = 0x88f0, // 10  001  0001  1110  000
+       A64SysReg_TRCRSCTLR15       = 0x88f8, // 10  001  0001  1111  000
+       A64SysReg_TRCRSCTLR16       = 0x8881, // 10  001  0001  0000  001
+       A64SysReg_TRCRSCTLR17       = 0x8889, // 10  001  0001  0001  001
+       A64SysReg_TRCRSCTLR18       = 0x8891, // 10  001  0001  0010  001
+       A64SysReg_TRCRSCTLR19       = 0x8899, // 10  001  0001  0011  001
+       A64SysReg_TRCRSCTLR20       = 0x88a1, // 10  001  0001  0100  001
+       A64SysReg_TRCRSCTLR21       = 0x88a9, // 10  001  0001  0101  001
+       A64SysReg_TRCRSCTLR22       = 0x88b1, // 10  001  0001  0110  001
+       A64SysReg_TRCRSCTLR23       = 0x88b9, // 10  001  0001  0111  001
+       A64SysReg_TRCRSCTLR24       = 0x88c1, // 10  001  0001  1000  001
+       A64SysReg_TRCRSCTLR25       = 0x88c9, // 10  001  0001  1001  001
+       A64SysReg_TRCRSCTLR26       = 0x88d1, // 10  001  0001  1010  001
+       A64SysReg_TRCRSCTLR27       = 0x88d9, // 10  001  0001  1011  001
+       A64SysReg_TRCRSCTLR28       = 0x88e1, // 10  001  0001  1100  001
+       A64SysReg_TRCRSCTLR29       = 0x88e9, // 10  001  0001  1101  001
+       A64SysReg_TRCRSCTLR30       = 0x88f1, // 10  001  0001  1110  001
+       A64SysReg_TRCRSCTLR31       = 0x88f9, // 10  001  0001  1111  001
+       A64SysReg_TRCSSCCR0         = 0x8882, // 10  001  0001  0000  010
+       A64SysReg_TRCSSCCR1         = 0x888a, // 10  001  0001  0001  010
+       A64SysReg_TRCSSCCR2         = 0x8892, // 10  001  0001  0010  010
+       A64SysReg_TRCSSCCR3         = 0x889a, // 10  001  0001  0011  010
+       A64SysReg_TRCSSCCR4         = 0x88a2, // 10  001  0001  0100  010
+       A64SysReg_TRCSSCCR5         = 0x88aa, // 10  001  0001  0101  010
+       A64SysReg_TRCSSCCR6         = 0x88b2, // 10  001  0001  0110  010
+       A64SysReg_TRCSSCCR7         = 0x88ba, // 10  001  0001  0111  010
+       A64SysReg_TRCSSCSR0         = 0x88c2, // 10  001  0001  1000  010
+       A64SysReg_TRCSSCSR1         = 0x88ca, // 10  001  0001  1001  010
+       A64SysReg_TRCSSCSR2         = 0x88d2, // 10  001  0001  1010  010
+       A64SysReg_TRCSSCSR3         = 0x88da, // 10  001  0001  1011  010
+       A64SysReg_TRCSSCSR4         = 0x88e2, // 10  001  0001  1100  010
+       A64SysReg_TRCSSCSR5         = 0x88ea, // 10  001  0001  1101  010
+       A64SysReg_TRCSSCSR6         = 0x88f2, // 10  001  0001  1110  010
+       A64SysReg_TRCSSCSR7         = 0x88fa, // 10  001  0001  1111  010
+       A64SysReg_TRCSSPCICR0       = 0x8883, // 10  001  0001  0000  011
+       A64SysReg_TRCSSPCICR1       = 0x888b, // 10  001  0001  0001  011
+       A64SysReg_TRCSSPCICR2       = 0x8893, // 10  001  0001  0010  011
+       A64SysReg_TRCSSPCICR3       = 0x889b, // 10  001  0001  0011  011
+       A64SysReg_TRCSSPCICR4       = 0x88a3, // 10  001  0001  0100  011
+       A64SysReg_TRCSSPCICR5       = 0x88ab, // 10  001  0001  0101  011
+       A64SysReg_TRCSSPCICR6       = 0x88b3, // 10  001  0001  0110  011
+       A64SysReg_TRCSSPCICR7       = 0x88bb, // 10  001  0001  0111  011
+       A64SysReg_TRCPDCR           = 0x88a4, // 10  001  0001  0100  100
+       A64SysReg_TRCACVR0          = 0x8900, // 10  001  0010  0000  000
+       A64SysReg_TRCACVR1          = 0x8910, // 10  001  0010  0010  000
+       A64SysReg_TRCACVR2          = 0x8920, // 10  001  0010  0100  000
+       A64SysReg_TRCACVR3          = 0x8930, // 10  001  0010  0110  000
+       A64SysReg_TRCACVR4          = 0x8940, // 10  001  0010  1000  000
+       A64SysReg_TRCACVR5          = 0x8950, // 10  001  0010  1010  000
+       A64SysReg_TRCACVR6          = 0x8960, // 10  001  0010  1100  000
+       A64SysReg_TRCACVR7          = 0x8970, // 10  001  0010  1110  000
+       A64SysReg_TRCACVR8          = 0x8901, // 10  001  0010  0000  001
+       A64SysReg_TRCACVR9          = 0x8911, // 10  001  0010  0010  001
+       A64SysReg_TRCACVR10         = 0x8921, // 10  001  0010  0100  001
+       A64SysReg_TRCACVR11         = 0x8931, // 10  001  0010  0110  001
+       A64SysReg_TRCACVR12         = 0x8941, // 10  001  0010  1000  001
+       A64SysReg_TRCACVR13         = 0x8951, // 10  001  0010  1010  001
+       A64SysReg_TRCACVR14         = 0x8961, // 10  001  0010  1100  001
+       A64SysReg_TRCACVR15         = 0x8971, // 10  001  0010  1110  001
+       A64SysReg_TRCACATR0         = 0x8902, // 10  001  0010  0000  010
+       A64SysReg_TRCACATR1         = 0x8912, // 10  001  0010  0010  010
+       A64SysReg_TRCACATR2         = 0x8922, // 10  001  0010  0100  010
+       A64SysReg_TRCACATR3         = 0x8932, // 10  001  0010  0110  010
+       A64SysReg_TRCACATR4         = 0x8942, // 10  001  0010  1000  010
+       A64SysReg_TRCACATR5         = 0x8952, // 10  001  0010  1010  010
+       A64SysReg_TRCACATR6         = 0x8962, // 10  001  0010  1100  010
+       A64SysReg_TRCACATR7         = 0x8972, // 10  001  0010  1110  010
+       A64SysReg_TRCACATR8         = 0x8903, // 10  001  0010  0000  011
+       A64SysReg_TRCACATR9         = 0x8913, // 10  001  0010  0010  011
+       A64SysReg_TRCACATR10        = 0x8923, // 10  001  0010  0100  011
+       A64SysReg_TRCACATR11        = 0x8933, // 10  001  0010  0110  011
+       A64SysReg_TRCACATR12        = 0x8943, // 10  001  0010  1000  011
+       A64SysReg_TRCACATR13        = 0x8953, // 10  001  0010  1010  011
+       A64SysReg_TRCACATR14        = 0x8963, // 10  001  0010  1100  011
+       A64SysReg_TRCACATR15        = 0x8973, // 10  001  0010  1110  011
+       A64SysReg_TRCDVCVR0         = 0x8904, // 10  001  0010  0000  100
+       A64SysReg_TRCDVCVR1         = 0x8924, // 10  001  0010  0100  100
+       A64SysReg_TRCDVCVR2         = 0x8944, // 10  001  0010  1000  100
+       A64SysReg_TRCDVCVR3         = 0x8964, // 10  001  0010  1100  100
+       A64SysReg_TRCDVCVR4         = 0x8905, // 10  001  0010  0000  101
+       A64SysReg_TRCDVCVR5         = 0x8925, // 10  001  0010  0100  101
+       A64SysReg_TRCDVCVR6         = 0x8945, // 10  001  0010  1000  101
+       A64SysReg_TRCDVCVR7         = 0x8965, // 10  001  0010  1100  101
+       A64SysReg_TRCDVCMR0         = 0x8906, // 10  001  0010  0000  110
+       A64SysReg_TRCDVCMR1         = 0x8926, // 10  001  0010  0100  110
+       A64SysReg_TRCDVCMR2         = 0x8946, // 10  001  0010  1000  110
+       A64SysReg_TRCDVCMR3         = 0x8966, // 10  001  0010  1100  110
+       A64SysReg_TRCDVCMR4         = 0x8907, // 10  001  0010  0000  111
+       A64SysReg_TRCDVCMR5         = 0x8927, // 10  001  0010  0100  111
+       A64SysReg_TRCDVCMR6         = 0x8947, // 10  001  0010  1000  111
+       A64SysReg_TRCDVCMR7         = 0x8967, // 10  001  0010  1100  111
+       A64SysReg_TRCCIDCVR0        = 0x8980, // 10  001  0011  0000  000
+       A64SysReg_TRCCIDCVR1        = 0x8990, // 10  001  0011  0010  000
+       A64SysReg_TRCCIDCVR2        = 0x89a0, // 10  001  0011  0100  000
+       A64SysReg_TRCCIDCVR3        = 0x89b0, // 10  001  0011  0110  000
+       A64SysReg_TRCCIDCVR4        = 0x89c0, // 10  001  0011  1000  000
+       A64SysReg_TRCCIDCVR5        = 0x89d0, // 10  001  0011  1010  000
+       A64SysReg_TRCCIDCVR6        = 0x89e0, // 10  001  0011  1100  000
+       A64SysReg_TRCCIDCVR7        = 0x89f0, // 10  001  0011  1110  000
+       A64SysReg_TRCVMIDCVR0       = 0x8981, // 10  001  0011  0000  001
+       A64SysReg_TRCVMIDCVR1       = 0x8991, // 10  001  0011  0010  001
+       A64SysReg_TRCVMIDCVR2       = 0x89a1, // 10  001  0011  0100  001
+       A64SysReg_TRCVMIDCVR3       = 0x89b1, // 10  001  0011  0110  001
+       A64SysReg_TRCVMIDCVR4       = 0x89c1, // 10  001  0011  1000  001
+       A64SysReg_TRCVMIDCVR5       = 0x89d1, // 10  001  0011  1010  001
+       A64SysReg_TRCVMIDCVR6       = 0x89e1, // 10  001  0011  1100  001
+       A64SysReg_TRCVMIDCVR7       = 0x89f1, // 10  001  0011  1110  001
+       A64SysReg_TRCCIDCCTLR0      = 0x8982, // 10  001  0011  0000  010
+       A64SysReg_TRCCIDCCTLR1      = 0x898a, // 10  001  0011  0001  010
+       A64SysReg_TRCVMIDCCTLR0     = 0x8992, // 10  001  0011  0010  010
+       A64SysReg_TRCVMIDCCTLR1     = 0x899a, // 10  001  0011  0011  010
+       A64SysReg_TRCITCTRL         = 0x8b84, // 10  001  0111  0000  100
+       A64SysReg_TRCCLAIMSET       = 0x8bc6, // 10  001  0111  1000  110
+       A64SysReg_TRCCLAIMCLR       = 0x8bce, // 10  001  0111  1001  110
+
+       // GICv3 registers
+       A64SysReg_ICC_BPR1_EL1      = 0xc663, // 11  000  1100  1100  011
+       A64SysReg_ICC_BPR0_EL1      = 0xc643, // 11  000  1100  1000  011
+       A64SysReg_ICC_PMR_EL1       = 0xc230, // 11  000  0100  0110  000
+       A64SysReg_ICC_CTLR_EL1      = 0xc664, // 11  000  1100  1100  100
+       A64SysReg_ICC_CTLR_EL3      = 0xf664, // 11  110  1100  1100  100
+       A64SysReg_ICC_SRE_EL1       = 0xc665, // 11  000  1100  1100  101
+       A64SysReg_ICC_SRE_EL2       = 0xe64d, // 11  100  1100  1001  101
+       A64SysReg_ICC_SRE_EL3       = 0xf665, // 11  110  1100  1100  101
+       A64SysReg_ICC_IGRPEN0_EL1   = 0xc666, // 11  000  1100  1100  110
+       A64SysReg_ICC_IGRPEN1_EL1   = 0xc667, // 11  000  1100  1100  111
+       A64SysReg_ICC_IGRPEN1_EL3   = 0xf667, // 11  110  1100  1100  111
+       A64SysReg_ICC_SEIEN_EL1     = 0xc668, // 11  000  1100  1101  000
+       A64SysReg_ICC_AP0R0_EL1     = 0xc644, // 11  000  1100  1000  100
+       A64SysReg_ICC_AP0R1_EL1     = 0xc645, // 11  000  1100  1000  101
+       A64SysReg_ICC_AP0R2_EL1     = 0xc646, // 11  000  1100  1000  110
+       A64SysReg_ICC_AP0R3_EL1     = 0xc647, // 11  000  1100  1000  111
+       A64SysReg_ICC_AP1R0_EL1     = 0xc648, // 11  000  1100  1001  000
+       A64SysReg_ICC_AP1R1_EL1     = 0xc649, // 11  000  1100  1001  001
+       A64SysReg_ICC_AP1R2_EL1     = 0xc64a, // 11  000  1100  1001  010
+       A64SysReg_ICC_AP1R3_EL1     = 0xc64b, // 11  000  1100  1001  011
+       A64SysReg_ICH_AP0R0_EL2     = 0xe640, // 11  100  1100  1000  000
+       A64SysReg_ICH_AP0R1_EL2     = 0xe641, // 11  100  1100  1000  001
+       A64SysReg_ICH_AP0R2_EL2     = 0xe642, // 11  100  1100  1000  010
+       A64SysReg_ICH_AP0R3_EL2     = 0xe643, // 11  100  1100  1000  011
+       A64SysReg_ICH_AP1R0_EL2     = 0xe648, // 11  100  1100  1001  000
+       A64SysReg_ICH_AP1R1_EL2     = 0xe649, // 11  100  1100  1001  001
+       A64SysReg_ICH_AP1R2_EL2     = 0xe64a, // 11  100  1100  1001  010
+       A64SysReg_ICH_AP1R3_EL2     = 0xe64b, // 11  100  1100  1001  011
+       A64SysReg_ICH_HCR_EL2       = 0xe658, // 11  100  1100  1011  000
+       A64SysReg_ICH_MISR_EL2      = 0xe65a, // 11  100  1100  1011  010
+       A64SysReg_ICH_VMCR_EL2      = 0xe65f, // 11  100  1100  1011  111
+       A64SysReg_ICH_VSEIR_EL2     = 0xe64c, // 11  100  1100  1001  100
+       A64SysReg_ICH_LR0_EL2       = 0xe660, // 11  100  1100  1100  000
+       A64SysReg_ICH_LR1_EL2       = 0xe661, // 11  100  1100  1100  001
+       A64SysReg_ICH_LR2_EL2       = 0xe662, // 11  100  1100  1100  010
+       A64SysReg_ICH_LR3_EL2       = 0xe663, // 11  100  1100  1100  011
+       A64SysReg_ICH_LR4_EL2       = 0xe664, // 11  100  1100  1100  100
+       A64SysReg_ICH_LR5_EL2       = 0xe665, // 11  100  1100  1100  101
+       A64SysReg_ICH_LR6_EL2       = 0xe666, // 11  100  1100  1100  110
+       A64SysReg_ICH_LR7_EL2       = 0xe667, // 11  100  1100  1100  111
+       A64SysReg_ICH_LR8_EL2       = 0xe668, // 11  100  1100  1101  000
+       A64SysReg_ICH_LR9_EL2       = 0xe669, // 11  100  1100  1101  001
+       A64SysReg_ICH_LR10_EL2      = 0xe66a, // 11  100  1100  1101  010
+       A64SysReg_ICH_LR11_EL2      = 0xe66b, // 11  100  1100  1101  011
+       A64SysReg_ICH_LR12_EL2      = 0xe66c, // 11  100  1100  1101  100
+       A64SysReg_ICH_LR13_EL2      = 0xe66d, // 11  100  1100  1101  101
+       A64SysReg_ICH_LR14_EL2      = 0xe66e, // 11  100  1100  1101  110
+       A64SysReg_ICH_LR15_EL2      = 0xe66f  // 11  100  1100  1101  111
+};
+
+enum TLBIValues {
+       A64TLBI_Invalid = -1,          // Op0 Op1  CRn   CRm   Op2
+       A64TLBI_IPAS2E1IS    = 0x6401, // 01  100  1000  0000  001
+       A64TLBI_IPAS2LE1IS   = 0x6405, // 01  100  1000  0000  101
+       A64TLBI_VMALLE1IS    = 0x4418, // 01  000  1000  0011  000
+       A64TLBI_ALLE2IS      = 0x6418, // 01  100  1000  0011  000
+       A64TLBI_ALLE3IS      = 0x7418, // 01  110  1000  0011  000
+       A64TLBI_VAE1IS       = 0x4419, // 01  000  1000  0011  001
+       A64TLBI_VAE2IS       = 0x6419, // 01  100  1000  0011  001
+       A64TLBI_VAE3IS       = 0x7419, // 01  110  1000  0011  001
+       A64TLBI_ASIDE1IS     = 0x441a, // 01  000  1000  0011  010
+       A64TLBI_VAAE1IS      = 0x441b, // 01  000  1000  0011  011
+       A64TLBI_ALLE1IS      = 0x641c, // 01  100  1000  0011  100
+       A64TLBI_VALE1IS      = 0x441d, // 01  000  1000  0011  101
+       A64TLBI_VALE2IS      = 0x641d, // 01  100  1000  0011  101
+       A64TLBI_VALE3IS      = 0x741d, // 01  110  1000  0011  101
+       A64TLBI_VMALLS12E1IS = 0x641e, // 01  100  1000  0011  110
+       A64TLBI_VAALE1IS     = 0x441f, // 01  000  1000  0011  111
+       A64TLBI_IPAS2E1      = 0x6421, // 01  100  1000  0100  001
+       A64TLBI_IPAS2LE1     = 0x6425, // 01  100  1000  0100  101
+       A64TLBI_VMALLE1      = 0x4438, // 01  000  1000  0111  000
+       A64TLBI_ALLE2        = 0x6438, // 01  100  1000  0111  000
+       A64TLBI_ALLE3        = 0x7438, // 01  110  1000  0111  000
+       A64TLBI_VAE1         = 0x4439, // 01  000  1000  0111  001
+       A64TLBI_VAE2         = 0x6439, // 01  100  1000  0111  001
+       A64TLBI_VAE3         = 0x7439, // 01  110  1000  0111  001
+       A64TLBI_ASIDE1       = 0x443a, // 01  000  1000  0111  010
+       A64TLBI_VAAE1        = 0x443b, // 01  000  1000  0111  011
+       A64TLBI_ALLE1        = 0x643c, // 01  100  1000  0111  100
+       A64TLBI_VALE1        = 0x443d, // 01  000  1000  0111  101
+       A64TLBI_VALE2        = 0x643d, // 01  100  1000  0111  101
+       A64TLBI_VALE3        = 0x743d, // 01  110  1000  0111  101
+       A64TLBI_VMALLS12E1   = 0x643e, // 01  100  1000  0111  110
+       A64TLBI_VAALE1       = 0x443f  // 01  000  1000  0111  111
+};
+
+bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm);
+
+char *NamedImmMapper_toString(NamedImmMapper *N, uint32_t Value, bool *Valid);
+
+uint32_t NamedImmMapper_fromString(NamedImmMapper *N, char *Name, bool *Valid);
+
+bool NamedImmMapper_validImm(NamedImmMapper *N, uint32_t Value);
+
+void SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid, char *result);
+
+#endif
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
new file mode 100644 (file)
index 0000000..4b5eb70
--- /dev/null
@@ -0,0 +1,1638 @@
+//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the functions necessary to decode AArch64 instruction
+// bitpatterns into MCInsts (with the help of TableGenerated information from
+// the instruction definitions).
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h>     // DEBUG
+#include <stdlib.h>
+
+#include "../../cs_priv.h"
+
+#include "../../SubtargetFeature.h"
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+
+#include "AArch64BaseInfo.h"
+
+// Forward-declarations used in the auto-generated files.
+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+static DecodeStatus
+DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+static DecodeStatus
+DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
+               unsigned RegNo, uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeFPR128LoRegisterClass(MCInst *Inst,
+               unsigned RegNo, uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeGPR64noxzrRegisterClass(MCInst *Inst,
+               unsigned RegNo,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeQPairRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeDTripleRegisterClass(MCInst *Inst,
+               unsigned RegNo, uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeQTripleRegisterClass(MCInst *Inst,
+               unsigned RegNo, uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeDQuadRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeQQuadRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeAddrRegExtendOperand(MCInst *Inst,
+               unsigned OptionHiS,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeBitfield32ImmOperand(MCInst *Inst,
+               unsigned Imm6Bits,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeCVT32FixedPosOperand(MCInst *Inst,
+               unsigned Imm6Bits,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeFPZeroOperand(MCInst *Inst,
+               unsigned RmBits,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeShiftRightImm8(MCInst *Inst, unsigned Val,
+               uint64_t Address, void *Decoder);
+static DecodeStatus DecodeShiftRightImm16(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeShiftRightImm32(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeShiftRightImm64(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeShiftLeftImm8(MCInst *Inst, unsigned Val,
+               uint64_t Address, void *Decoder);
+static DecodeStatus DecodeShiftLeftImm16(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeShiftLeftImm32(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeShiftLeftImm64(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeMoveWideImmOperand(MCInst *Inst,
+               unsigned FullImm,
+               uint64_t Address,
+               void *Decoder, int RegWidth);
+
+static DecodeStatus DecodeLogicalImmOperand(MCInst *Inst,
+               unsigned Bits,
+               uint64_t Address,
+               void *Decoder, int RegWidth);
+
+static DecodeStatus DecodeRegExtendOperand(MCInst *Inst,
+               unsigned ShiftAmount,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus
+DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
+               uint64_t Address, void *Decoder, A64SE_ShiftExtSpecifiers Ext, bool IsHalf);
+
+static DecodeStatus Decode32BitShiftOperand(MCInst *Inst,
+               unsigned ShiftAmount,
+               uint64_t Address,
+               void *Decoder);
+static DecodeStatus DecodeBitfieldInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeLDSTPairInstruction(MCInst *Inst,
+               unsigned Insn,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeLoadPairExclusiveInstruction(MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeNamedImmOperand(MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder, NamedImmMapper *N);
+
+static DecodeStatus
+DecodeSysRegOperand(SysRegMapper *InstMapper,
+               MCInst *Inst, unsigned Val,
+               uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeMRSOperand(MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeMSROperand(MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeSingleIndexedInstruction(MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeVLDSTPostInstruction(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder);
+
+static DecodeStatus DecodeSHLLInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder);
+
+static bool Check(DecodeStatus *Out, DecodeStatus In);
+
+#define GET_SUBTARGETINFO_ENUM
+#include "AArch64GenSubtargetInfo.inc"
+
+// Hacky: enable all features for disassembler
+static uint64_t AArch64_getFeatureBits(void)
+{
+       // enable all features
+       return -1;
+}
+
+#include "AArch64GenDisassemblerTables.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "AArch64GenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+#include "AArch64GenRegisterInfo.inc"
+
+static bool Check(DecodeStatus *Out, DecodeStatus In)
+{
+       switch (In) {
+               case MCDisassembler_Success:
+                       // Out stays the same.
+                       return true;
+               case MCDisassembler_SoftFail:
+                       *Out = In;
+                       return true;
+               case MCDisassembler_Fail:
+                       *Out = In;
+                       return false;
+               default:
+                       return false;   // never reach
+       }
+}
+
+#define GET_REGINFO_MC_DESC
+#include "AArch64GenRegisterInfo.inc"
+void AArch64_init(MCRegisterInfo *MRI)
+{
+         /*
+         RI->InitMCRegisterInfo(AArch64RegDesc, 228,
+         RA, PC,
+         AArch64MCRegisterClasses, 15,
+         AArch64RegUnitRoots, 66,
+         AArch64RegDiffLists,
+         AArch64RegStrings,
+         AArch64SubRegIdxLists, 6,
+          AArch64SubRegIdxRanges,   AArch64RegEncodingTable);
+         */
+
+       /*
+       RI->InitMCRegisterInfo(AArch64RegDesc, 420,
+                       RA, PC,
+                       AArch64MCRegisterClasses, 61,
+                       AArch64RegUnitRoots, 66,
+                       AArch64RegDiffLists,
+                       AArch64RegStrings,
+                       AArch64SubRegIdxLists, 53,
+                       AArch64SubRegIdxRanges, AArch64RegEncodingTable);
+       */
+
+       MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420,
+                       0, 0, 
+                       AArch64MCRegisterClasses, 61,
+                       0, 0, 
+                       AArch64RegDiffLists,
+                       0, 
+                       AArch64SubRegIdxLists, 53,
+                       0);
+}
+
+
+static DecodeStatus _getInstruction(MCInst *MI,
+               const uint8_t *code, size_t code_len,
+               uint16_t *Size,
+               uint64_t Address, MCRegisterInfo *MRI)
+{
+       if (code_len < 4) {
+               // not enough data
+               *Size = 0;
+               return MCDisassembler_Fail;
+       }
+
+       // Encoded as a small-endian 32-bit word in the stream.
+       uint32_t insn = (code[3] << 24) | (code[2] << 16) |
+               (code[1] <<  8) | (code[0] <<  0);
+
+       //printf("insn: %u\n", insn);
+       // Calling the auto-generated decoder function.
+       DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, MRI);
+       //printf("result: %u\n", result);
+       if (result != MCDisassembler_Fail) {
+               *Size = 4;
+               return result;
+       }
+
+       MCInst_clear(MI);
+       *Size = 0;
+       return MCDisassembler_Fail;
+}
+
+bool AArch64_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info)
+{
+       DecodeStatus status = _getInstruction(instr,
+                       code, code_len,
+                       size,
+                       address, (MCRegisterInfo *)info);
+
+       return status == MCDisassembler_Success;
+}
+
+static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
+{
+       MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
+       return rc->RegsBegin[RegNo];
+}
+
+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_GPR64RegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_GPR64xspRegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_GPR32RegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_GPR32wspRegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_FPR8RegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_FPR16RegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+
+static DecodeStatus
+DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_FPR32RegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_FPR64RegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 15)
+               return MCDisassembler_Fail;
+
+       return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+static DecodeStatus
+DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_FPR128RegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR128LoRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address, void *Decoder)
+{
+       if (RegNo > 15)
+               return MCDisassembler_Fail;
+
+       return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+static DecodeStatus DecodeGPR64noxzrRegisterClass(MCInst *Inst,
+               unsigned RegNo,
+               uint64_t Address,
+               void *Decoder)
+{
+       if (RegNo > 30)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, AArch64_GPR64noxzrRegClassID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegisterClassByID(MCInst *Inst, unsigned RegNo,
+               unsigned RegID,
+               void *Decoder)
+{
+       if (RegNo > 31)
+               return MCDisassembler_Fail;
+
+       uint16_t Register = getReg(Decoder, RegID, RegNo);
+       MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder)
+{
+       return DecodeRegisterClassByID(Inst, RegNo, AArch64_DPairRegClassID,
+                       Decoder);
+}
+
+static DecodeStatus DecodeQPairRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder)
+{
+       return DecodeRegisterClassByID(Inst, RegNo, AArch64_QPairRegClassID,
+                       Decoder);
+}
+
+static DecodeStatus DecodeDTripleRegisterClass(MCInst *Inst,
+               unsigned RegNo, uint64_t Address,
+               void *Decoder)
+{
+       return DecodeRegisterClassByID(Inst, RegNo, AArch64_DTripleRegClassID,
+                       Decoder);
+}
+
+static DecodeStatus DecodeQTripleRegisterClass(MCInst *Inst,
+               unsigned RegNo, uint64_t Address,
+               void *Decoder)
+{
+       return DecodeRegisterClassByID(Inst, RegNo, AArch64_QTripleRegClassID,
+                       Decoder);
+}
+
+static DecodeStatus DecodeDQuadRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder)
+{
+       return DecodeRegisterClassByID(Inst, RegNo, AArch64_DQuadRegClassID,
+                       Decoder);
+}
+
+static DecodeStatus DecodeQQuadRegisterClass(MCInst *Inst, unsigned RegNo,
+               uint64_t Address,
+               void *Decoder)
+{
+       return DecodeRegisterClassByID(Inst, RegNo, AArch64_QQuadRegClassID,
+                       Decoder);
+}
+
+static DecodeStatus DecodeAddrRegExtendOperand(MCInst *Inst,
+               unsigned OptionHiS,
+               uint64_t Address,
+               void *Decoder)
+{
+       // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
+       // S}. Hence we want to check bit 1.
+       if (!(OptionHiS & 2))
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(OptionHiS));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBitfield32ImmOperand(MCInst *Inst,
+               unsigned Imm6Bits,
+               uint64_t Address,
+               void *Decoder)
+{
+       // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
+       // between 0 and 31.
+       if (Imm6Bits > 31)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Imm6Bits));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCVT32FixedPosOperand(MCInst *Inst,
+               unsigned Imm6Bits,
+               uint64_t Address,
+               void *Decoder)
+{
+       // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
+       if (Imm6Bits < 32)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Imm6Bits));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFPZeroOperand(MCInst *Inst,
+               unsigned RmBits, uint64_t Address, void *Decoder)
+{
+       // Any bits are valid in the instruction (they're architecturally ignored),
+       // but a code generator should insert 0.
+       MCInst_addOperand(Inst, MCOperand_CreateImm(0));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftRightImm8(MCInst *Inst,
+               unsigned Val, uint64_t Address, void *Decoder)
+{
+       MCInst_addOperand(Inst, MCOperand_CreateImm(8 - Val));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftRightImm16(MCInst *Inst,
+               unsigned Val, uint64_t Address, void *Decoder)
+{
+       MCInst_addOperand(Inst, MCOperand_CreateImm(16 - Val));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftRightImm32(MCInst *Inst,
+               unsigned Val, uint64_t Address, void *Decoder)
+{
+       MCInst_addOperand(Inst, MCOperand_CreateImm(32 - Val));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftRightImm64(MCInst *Inst,
+               unsigned Val, uint64_t Address, void *Decoder)
+{
+       MCInst_addOperand(Inst, MCOperand_CreateImm(64 - Val));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftLeftImm8(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder)
+{
+       if (Val > 7)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftLeftImm16(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder)
+{
+       if (Val > 15)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftLeftImm32(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder)
+{
+       if (Val > 31)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftLeftImm64(MCInst *Inst, unsigned Val,
+               uint64_t Address,
+               void *Decoder)
+{
+       if (Val > 63)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMoveWideImmOperand(MCInst *Inst,
+               unsigned FullImm,
+               uint64_t Address,
+               void *Decoder, int RegWidth)
+{
+       unsigned Imm16 = FullImm & 0xffff;
+       unsigned Shift = FullImm >> 16;
+
+       if (RegWidth == 32 && Shift > 1) return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Imm16));
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Shift));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLogicalImmOperand(MCInst *Inst,
+               unsigned Bits,
+               uint64_t Address,
+               void *Decoder, int RegWidth)
+{
+       uint64_t Imm;
+       if (!A64Imms_isLogicalImmBits(RegWidth, Bits, &Imm))
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Bits));
+       return MCDisassembler_Success;
+}
+
+
+static DecodeStatus DecodeRegExtendOperand(MCInst *Inst,
+               unsigned ShiftAmount,
+               uint64_t Address,
+               void *Decoder)
+{
+       // Only values 0-4 are valid for this 3-bit field
+       if (ShiftAmount > 4)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(ShiftAmount));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus Decode32BitShiftOperand(MCInst *Inst,
+               unsigned ShiftAmount,
+               uint64_t Address,
+               void *Decoder)
+{
+       // Only values below 32 are valid for a 32-bit register
+       if (ShiftAmount > 31)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(ShiftAmount));
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBitfieldInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder)
+{
+       unsigned Rd = fieldFromInstruction(Insn, 0, 5);
+       unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+       unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
+       unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
+       unsigned SF = fieldFromInstruction(Insn, 31, 1);
+
+       // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
+       // out assertions that it thinks should never be hit.
+       enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
+       Opc = (enum OpcTypes)fieldFromInstruction(Insn, 29, 2);
+
+       if (!SF) {
+               // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
+               if (ImmR > 31 || ImmS > 31)
+                       return MCDisassembler_Fail;
+       }
+
+       if (SF) {
+               DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
+               // BFM MCInsts use Rd as a source too.
+               if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
+               DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
+       } else {
+               DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
+               // BFM MCInsts use Rd as a source too.
+               if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
+               DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
+       }
+
+       // ASR and LSR have more specific patterns so they won't get here:
+       //assert(!(ImmS == 31 && !SF && Opc != BFM)
+       //       && "shift should have used auto decode");
+       //assert(!(ImmS == 63 && SF && Opc != BFM)
+       //       && "shift should have used auto decode");
+
+       // Extension instructions similarly:
+       if (Opc == SBFM && ImmR == 0) {
+               //assert((ImmS != 7 && ImmS != 15) && "extension got here");
+               //assert((ImmS != 31 || SF == 0) && "extension got here");
+       } else if (Opc == UBFM && ImmR == 0) {
+               //assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
+       }
+
+       if (Opc == UBFM) {
+               // It might be a LSL instruction, which actually takes the shift amount
+               // itself as an MCInst operand.
+               if (SF && (ImmS + 1) % 64 == ImmR) {
+                       MCInst_setOpcode(Inst, AArch64_LSLxxi);
+                       MCInst_addOperand(Inst, MCOperand_CreateImm(63 - ImmS));
+                       return MCDisassembler_Success;
+               } else if (!SF && (ImmS + 1) % 32 == ImmR) {
+                       MCInst_setOpcode(Inst, AArch64_LSLwwi);
+                       MCInst_addOperand(Inst, MCOperand_CreateImm(31 - ImmS));
+                       return MCDisassembler_Success;
+               }
+       }
+
+       // Otherwise it's definitely either an extract or an insert depending on which
+       // of ImmR or ImmS is larger.
+       unsigned ExtractOp = 0, InsertOp = 0;
+       switch (Opc) {
+               default: break; // never reach
+               case SBFM:
+                                ExtractOp = SF ? AArch64_SBFXxxii : AArch64_SBFXwwii;
+                                InsertOp = SF ? AArch64_SBFIZxxii : AArch64_SBFIZwwii;
+                                break;
+               case BFM:
+                                ExtractOp = SF ? AArch64_BFXILxxii : AArch64_BFXILwwii;
+                                InsertOp = SF ? AArch64_BFIxxii : AArch64_BFIwwii;
+                                break;
+               case UBFM:
+                                ExtractOp = SF ? AArch64_UBFXxxii : AArch64_UBFXwwii;
+                                InsertOp = SF ? AArch64_UBFIZxxii : AArch64_UBFIZwwii;
+                                break;
+       }
+
+       // Otherwise it's a boring insert or extract
+       MCInst_addOperand(Inst, MCOperand_CreateImm(ImmR));
+       MCInst_addOperand(Inst, MCOperand_CreateImm(ImmS));
+
+
+       if (ImmS < ImmR)
+               MCInst_setOpcode(Inst, InsertOp);
+       else
+               MCInst_setOpcode(Inst, ExtractOp);
+
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder)
+{
+       // This decoder exists to add the dummy Lane operand to the MCInst, which must
+       // be 1 in assembly but has no other real manifestation.
+       unsigned Rd = fieldFromInstruction(Insn, 0, 5);
+       unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+       unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
+
+       if (IsToVec) {
+               DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
+               DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
+       } else {
+               DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
+               DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
+       }
+
+       // Add the lane
+       MCInst_addOperand(Inst, MCOperand_CreateImm(1));
+
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLDSTPairInstruction(MCInst *Inst,
+               unsigned Insn,
+               uint64_t Address,
+               void *Decoder)
+{
+       DecodeStatus Result = MCDisassembler_Success;
+       unsigned Rt = fieldFromInstruction(Insn, 0, 5);
+       unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+       unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
+       unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
+       unsigned L = fieldFromInstruction(Insn, 22, 1);
+       unsigned V = fieldFromInstruction(Insn, 26, 1);
+       unsigned Opc = fieldFromInstruction(Insn, 30, 2);
+
+       // Not an official name, but it turns out that bit 23 distinguishes indexed
+       // from non-indexed operations.
+       unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
+
+       if (Indexed && L == 0) {
+               // The MCInst for an indexed store has an out operand and 4 ins:
+               //    Rn_wb, Rt, Rt2, Rn, Imm
+               DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+       }
+
+       // You shouldn't load to the same register twice in an instruction...
+       if (L && Rt == Rt2)
+               Result = MCDisassembler_SoftFail;
+
+       // ... or do any operation that writes-back to a transfer register. But note
+       // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
+       if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
+               Result = MCDisassembler_SoftFail;
+
+       // Exactly how we decode the MCInst's registers depends on the Opc and V
+       // fields of the instruction. These also obviously determine the size of the
+       // operation so we can fill in that information while we're at it.
+       if (V) {
+               // The instruction operates on the FP/SIMD registers
+               switch (Opc) {
+                       default: return MCDisassembler_Fail;
+                       case 0:
+                                        DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
+                                        DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
+                                        break;
+                       case 1:
+                                        DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
+                                        DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
+                                        break;
+                       case 2:
+                                        DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
+                                        DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
+                                        break;
+               }
+       } else {
+               switch (Opc) {
+                       default: return MCDisassembler_Fail;
+                       case 0:
+                                        DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
+                                        DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
+                                        break;
+                       case 1:
+                                        //assert(L && "unexpected \"store signed\" attempt");
+                                        DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
+                                        DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
+                                        break;
+                       case 2:
+                                        DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
+                                        DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
+                                        break;
+               }
+       }
+
+       if (Indexed && L == 1) {
+               // The MCInst for an indexed load has 3 out operands and an 3 ins:
+               //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
+               DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+       }
+
+
+       DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+       MCInst_addOperand(Inst, MCOperand_CreateImm(SImm7));
+
+       return Result;
+}
+
+static DecodeStatus DecodeLoadPairExclusiveInstruction(MCInst *Inst,
+               uint32_t Val,
+               uint64_t Address,
+               void *Decoder)
+{
+       unsigned Rt = fieldFromInstruction(Val, 0, 5);
+       unsigned Rn = fieldFromInstruction(Val, 5, 5);
+       unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
+       unsigned MemSize = fieldFromInstruction(Val, 30, 2);
+
+       DecodeStatus S = MCDisassembler_Success;
+       if (Rt == Rt2) S = MCDisassembler_SoftFail;
+
+       switch (MemSize) {
+               case 2:
+                       if (!Check(&S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
+                               return MCDisassembler_Fail;
+                       if (!Check(&S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
+                               return MCDisassembler_Fail;
+                       break;
+               case 3:
+                       if (!Check(&S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
+                               return MCDisassembler_Fail;
+                       if (!Check(&S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
+                               return MCDisassembler_Fail;
+                       break;
+               default:
+                       break;  // never reach
+       }
+
+       if (!Check(&S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
+               return MCDisassembler_Fail;
+
+       return S;
+}
+
+static DecodeStatus DecodeNamedImmOperand(MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder, NamedImmMapper *N)
+{
+       bool ValidNamed;
+
+       NamedImmMapper_toString(N, Val, &ValidNamed);
+       if (ValidNamed || NamedImmMapper_validImm(N, Val)) {
+               MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
+               return MCDisassembler_Success;
+       }
+
+       return MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeSysRegOperand(SysRegMapper *Mapper,
+               MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder)
+{
+       bool ValidNamed;
+       char result[128];
+       SysRegMapper_toString(Mapper, Val, &ValidNamed, result);
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
+
+       return ValidNamed ? MCDisassembler_Success : MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeMRSOperand(MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder)
+{
+       return DecodeSysRegOperand(&AArch64_MRSMapper, Inst, Val, Address, Decoder);
+}
+
+static DecodeStatus DecodeMSROperand(MCInst *Inst,
+               unsigned Val,
+               uint64_t Address,
+               void *Decoder)
+{
+       return DecodeSysRegOperand(&AArch64_MSRMapper, Inst, Val, Address, Decoder);
+}
+
+static DecodeStatus DecodeSingleIndexedInstruction(MCInst *Inst,
+               unsigned Insn,
+               uint64_t Address,
+               void *Decoder)
+{
+       unsigned Rt = fieldFromInstruction(Insn, 0, 5);
+       unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+       unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
+
+       unsigned Opc = fieldFromInstruction(Insn, 22, 2);
+       unsigned V = fieldFromInstruction(Insn, 26, 1);
+       unsigned Size = fieldFromInstruction(Insn, 30, 2);
+
+       if (Opc == 0 || (V == 1 && Opc == 2)) {
+               // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
+               DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+       }
+
+       if (V == 0 && (Opc == 2 || Size == 3)) {
+               DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
+       } else if (V == 0) {
+               DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
+       } else if (V == 1 && (Opc & 2)) {
+               DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
+       } else {
+               switch (Size) {
+                       case 0:
+                               DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 1:
+                               DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 2:
+                               DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 3:
+                               DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+               }
+       }
+
+       if (Opc != 0 && (V != 1 || Opc != 2)) {
+               // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
+               DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+       }
+
+       DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(Imm9));
+
+       // N.b. The official documentation says undpredictable if Rt == Rn, but this
+       // takes place at the architectural rather than encoding level:
+       //
+       // "STR xzr, [sp], #4" is perfectly valid.
+       if (V == 0 && Rt == Rn && Rn != 31)
+               return MCDisassembler_SoftFail;
+       else
+               return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
+               uint64_t Address, void *Decoder, A64SE_ShiftExtSpecifiers Ext, bool IsHalf)
+{
+       bool IsLSL = false;
+       if (Ext == A64SE_LSL)
+               IsLSL = true;
+       else if (Ext != A64SE_MSL)
+               return MCDisassembler_Fail;
+
+       // MSL and LSLH accepts encoded shift amount 0 or 1.
+       if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
+               return MCDisassembler_Fail;
+
+       // LSL  accepts encoded shift amount 0, 1, 2 or 3.
+       if (IsLSL && ShiftAmount > 3)
+               return MCDisassembler_Fail;
+
+       MCInst_addOperand(Inst, MCOperand_CreateImm(ShiftAmount));
+       return MCDisassembler_Success;
+}
+
+// Decode post-index vector load/store instructions.
+// This is necessary as we need to decode Rm: if Rm == 0b11111, the last
+// operand is an immediate equal the the length of vector list in bytes,
+// or Rm is decoded to a GPR64noxzr register.
+static DecodeStatus DecodeVLDSTPostInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder)
+{
+       unsigned Rt = fieldFromInstruction(Insn, 0, 5);
+       unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+       unsigned Rm = fieldFromInstruction(Insn, 16, 5);
+       unsigned Opcode = fieldFromInstruction(Insn, 12, 4);
+       unsigned IsLoad = fieldFromInstruction(Insn, 22, 1);
+       // 0 for 64bit vector list, 1 for 128bit vector list
+       unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1);
+
+       unsigned NumVecs;
+       switch (Opcode) {
+               default:
+                       // llvm_unreachable("Invalid opcode for post-index load/store instructions");
+               case 0: // ld4/st4
+               case 2: // ld1/st1 with 4 vectors
+                       NumVecs = 4; break;
+               case 4: // ld3/st3
+               case 6: // ld1/st1 with 3 vectors
+                       NumVecs = 3; break;
+               case 7: // ld1/st1 with 1 vector
+                       NumVecs = 1; break;
+               case 8:  // ld2/st2
+               case 10: // ld1/st1 with 2 vectors
+                       NumVecs = 2; break;
+       }
+
+       // Decode vector list of 1/2/3/4 vectors for load instructions.
+       if (IsLoad) {
+               switch (NumVecs) {
+                       case 1:
+                               Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 2:
+                               Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 3:
+                               Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 4:
+                               Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+               }
+       }
+
+       // Decode write back register, which is equal to Rn.
+       DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+       DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+
+       if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte
+               MCInst_addOperand(Inst, MCOperand_CreateImm(NumVecs * (Is128BitVec ? 16 : 8)));
+       else // Decode Rm
+               DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
+
+       // Decode vector list of 1/2/3/4 vectors for load instructions.
+       if (!IsLoad) {
+               switch (NumVecs) {
+                       case 1:
+                               Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 2:
+                               Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 3:
+                               Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 4:
+                               Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+               }
+       }
+
+       return MCDisassembler_Success;
+}
+
+// Decode post-index vector load/store lane instructions.
+// This is necessary as we need to decode Rm: if Rm == 0b11111, the last
+// operand is an immediate equal the the length of the changed bytes,
+// or Rm is decoded to a GPR64noxzr register.
+static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder)
+{
+       bool Is64bitVec = false;
+       bool IsLoadDup = false;
+       bool IsLoad = false;
+       // The total number of bytes transferred.
+       // TransferBytes = NumVecs * OneLaneBytes
+       unsigned TransferBytes = 0;
+       unsigned NumVecs = 0;
+       unsigned Opc = MCInst_getOpcode(Inst);
+       switch (Opc) {
+               case AArch64_LD1R_WB_8B_fixed: case AArch64_LD1R_WB_8B_register:
+               case AArch64_LD1R_WB_4H_fixed: case AArch64_LD1R_WB_4H_register:
+               case AArch64_LD1R_WB_2S_fixed: case AArch64_LD1R_WB_2S_register:
+               case AArch64_LD1R_WB_1D_fixed: case AArch64_LD1R_WB_1D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD1R_WB_8B_fixed: case AArch64_LD1R_WB_8B_register:
+                                               TransferBytes = 1; break;
+                                       case AArch64_LD1R_WB_4H_fixed: case AArch64_LD1R_WB_4H_register:
+                                               TransferBytes = 2; break;
+                                       case AArch64_LD1R_WB_2S_fixed: case AArch64_LD1R_WB_2S_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD1R_WB_1D_fixed: case AArch64_LD1R_WB_1D_register:
+                                               TransferBytes = 8; break;
+                               }
+                               Is64bitVec = true;
+                               IsLoadDup = true;
+                               NumVecs = 1;
+                               break;
+                       }
+
+               case AArch64_LD1R_WB_16B_fixed: case AArch64_LD1R_WB_16B_register:
+               case AArch64_LD1R_WB_8H_fixed: case AArch64_LD1R_WB_8H_register:
+               case AArch64_LD1R_WB_4S_fixed: case AArch64_LD1R_WB_4S_register:
+               case AArch64_LD1R_WB_2D_fixed: case AArch64_LD1R_WB_2D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD1R_WB_16B_fixed: case AArch64_LD1R_WB_16B_register:
+                                               TransferBytes = 1; break;
+                                       case AArch64_LD1R_WB_8H_fixed: case AArch64_LD1R_WB_8H_register:
+                                               TransferBytes = 2; break;
+                                       case AArch64_LD1R_WB_4S_fixed: case AArch64_LD1R_WB_4S_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD1R_WB_2D_fixed: case AArch64_LD1R_WB_2D_register:
+                                               TransferBytes = 8; break;
+                               }
+                               IsLoadDup = true;
+                               NumVecs = 1;
+                               break;
+                       }
+
+               case AArch64_LD2R_WB_8B_fixed: case AArch64_LD2R_WB_8B_register:
+               case AArch64_LD2R_WB_4H_fixed: case AArch64_LD2R_WB_4H_register:
+               case AArch64_LD2R_WB_2S_fixed: case AArch64_LD2R_WB_2S_register:
+               case AArch64_LD2R_WB_1D_fixed: case AArch64_LD2R_WB_1D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD2R_WB_8B_fixed: case AArch64_LD2R_WB_8B_register:
+                                               TransferBytes = 2; break;
+                                       case AArch64_LD2R_WB_4H_fixed: case AArch64_LD2R_WB_4H_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD2R_WB_2S_fixed: case AArch64_LD2R_WB_2S_register:
+                                               TransferBytes = 8; break;
+                                       case AArch64_LD2R_WB_1D_fixed: case AArch64_LD2R_WB_1D_register:
+                                               TransferBytes = 16; break;
+                               }
+                               Is64bitVec = true;
+                               IsLoadDup = true;
+                               NumVecs = 2;
+                               break;
+                       }
+
+               case AArch64_LD2R_WB_16B_fixed: case AArch64_LD2R_WB_16B_register:
+               case AArch64_LD2R_WB_8H_fixed: case AArch64_LD2R_WB_8H_register:
+               case AArch64_LD2R_WB_4S_fixed: case AArch64_LD2R_WB_4S_register:
+               case AArch64_LD2R_WB_2D_fixed: case AArch64_LD2R_WB_2D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD2R_WB_16B_fixed: case AArch64_LD2R_WB_16B_register:
+                                               TransferBytes = 2; break;
+                                       case AArch64_LD2R_WB_8H_fixed: case AArch64_LD2R_WB_8H_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD2R_WB_4S_fixed: case AArch64_LD2R_WB_4S_register:
+                                               TransferBytes = 8; break;
+                                       case AArch64_LD2R_WB_2D_fixed: case AArch64_LD2R_WB_2D_register:
+                                               TransferBytes = 16; break;
+                               }
+                               IsLoadDup = true;
+                               NumVecs = 2;
+                               break;
+                       }
+
+               case AArch64_LD3R_WB_8B_fixed: case AArch64_LD3R_WB_8B_register:
+               case AArch64_LD3R_WB_4H_fixed: case AArch64_LD3R_WB_4H_register:
+               case AArch64_LD3R_WB_2S_fixed: case AArch64_LD3R_WB_2S_register:
+               case AArch64_LD3R_WB_1D_fixed: case AArch64_LD3R_WB_1D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD3R_WB_8B_fixed: case AArch64_LD3R_WB_8B_register:
+                                               TransferBytes = 3; break;
+                                       case AArch64_LD3R_WB_4H_fixed: case AArch64_LD3R_WB_4H_register:
+                                               TransferBytes = 6; break;
+                                       case AArch64_LD3R_WB_2S_fixed: case AArch64_LD3R_WB_2S_register:
+                                               TransferBytes = 12; break;
+                                       case AArch64_LD3R_WB_1D_fixed: case AArch64_LD3R_WB_1D_register:
+                                               TransferBytes = 24; break;
+                               }
+                               Is64bitVec = true;
+                               IsLoadDup = true;
+                               NumVecs = 3;
+                               break;
+                       }
+
+               case AArch64_LD3R_WB_16B_fixed: case AArch64_LD3R_WB_16B_register:
+               case AArch64_LD3R_WB_4S_fixed: case AArch64_LD3R_WB_8H_register:
+               case AArch64_LD3R_WB_8H_fixed: case AArch64_LD3R_WB_4S_register:
+               case AArch64_LD3R_WB_2D_fixed: case AArch64_LD3R_WB_2D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD3R_WB_16B_fixed: case AArch64_LD3R_WB_16B_register:
+                                               TransferBytes = 3; break;
+                                       case AArch64_LD3R_WB_8H_fixed: case AArch64_LD3R_WB_8H_register:
+                                               TransferBytes = 6; break;
+                                       case AArch64_LD3R_WB_4S_fixed: case AArch64_LD3R_WB_4S_register:
+                                               TransferBytes = 12; break;
+                                       case AArch64_LD3R_WB_2D_fixed: case AArch64_LD3R_WB_2D_register:
+                                               TransferBytes = 24; break;
+                               }
+                               IsLoadDup = true;
+                               NumVecs = 3;
+                               break;
+                       }
+
+               case AArch64_LD4R_WB_8B_fixed: case AArch64_LD4R_WB_8B_register:
+               case AArch64_LD4R_WB_4H_fixed: case AArch64_LD4R_WB_4H_register:
+               case AArch64_LD4R_WB_2S_fixed: case AArch64_LD4R_WB_2S_register:
+               case AArch64_LD4R_WB_1D_fixed: case AArch64_LD4R_WB_1D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD4R_WB_8B_fixed: case AArch64_LD4R_WB_8B_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD4R_WB_4H_fixed: case AArch64_LD4R_WB_4H_register:
+                                               TransferBytes = 8; break;
+                                       case AArch64_LD4R_WB_2S_fixed: case AArch64_LD4R_WB_2S_register:
+                                               TransferBytes = 16; break;
+                                       case AArch64_LD4R_WB_1D_fixed: case AArch64_LD4R_WB_1D_register:
+                                               TransferBytes = 32; break;
+                               }
+                               Is64bitVec = true;
+                               IsLoadDup = true;
+                               NumVecs = 4;
+                               break;
+                       }
+
+               case AArch64_LD4R_WB_16B_fixed: case AArch64_LD4R_WB_16B_register:
+               case AArch64_LD4R_WB_4S_fixed: case AArch64_LD4R_WB_8H_register:
+               case AArch64_LD4R_WB_8H_fixed: case AArch64_LD4R_WB_4S_register:
+               case AArch64_LD4R_WB_2D_fixed: case AArch64_LD4R_WB_2D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD4R_WB_16B_fixed: case AArch64_LD4R_WB_16B_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD4R_WB_8H_fixed: case AArch64_LD4R_WB_8H_register:
+                                               TransferBytes = 8; break;
+                                       case AArch64_LD4R_WB_4S_fixed: case AArch64_LD4R_WB_4S_register:
+                                               TransferBytes = 16; break;
+                                       case AArch64_LD4R_WB_2D_fixed: case AArch64_LD4R_WB_2D_register:
+                                               TransferBytes = 32; break;
+                               }
+                               IsLoadDup = true;
+                               NumVecs = 4;
+                               break;
+                       }
+
+               case AArch64_LD1LN_WB_B_fixed: case AArch64_LD1LN_WB_B_register:
+               case AArch64_LD1LN_WB_H_fixed: case AArch64_LD1LN_WB_H_register:
+               case AArch64_LD1LN_WB_S_fixed: case AArch64_LD1LN_WB_S_register:
+               case AArch64_LD1LN_WB_D_fixed: case AArch64_LD1LN_WB_D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD1LN_WB_B_fixed: case AArch64_LD1LN_WB_B_register:
+                                               TransferBytes = 1; break;
+                                       case AArch64_LD1LN_WB_H_fixed: case AArch64_LD1LN_WB_H_register:
+                                               TransferBytes = 2; break;
+                                       case AArch64_LD1LN_WB_S_fixed: case AArch64_LD1LN_WB_S_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD1LN_WB_D_fixed: case AArch64_LD1LN_WB_D_register:
+                                               TransferBytes = 8; break;
+                               }
+                               IsLoad = true;
+                               NumVecs = 1;
+                               break;
+                       }
+
+               case AArch64_LD2LN_WB_B_fixed: case AArch64_LD2LN_WB_B_register:
+               case AArch64_LD2LN_WB_H_fixed: case AArch64_LD2LN_WB_H_register:
+               case AArch64_LD2LN_WB_S_fixed: case AArch64_LD2LN_WB_S_register:
+               case AArch64_LD2LN_WB_D_fixed: case AArch64_LD2LN_WB_D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD2LN_WB_B_fixed: case AArch64_LD2LN_WB_B_register:
+                                               TransferBytes = 2; break;
+                                       case AArch64_LD2LN_WB_H_fixed: case AArch64_LD2LN_WB_H_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD2LN_WB_S_fixed: case AArch64_LD2LN_WB_S_register:
+                                               TransferBytes = 8; break;
+                                       case AArch64_LD2LN_WB_D_fixed: case AArch64_LD2LN_WB_D_register:
+                                               TransferBytes = 16; break;
+                               }
+                               IsLoad = true;
+                               NumVecs = 2;
+                               break;
+                       }
+
+               case AArch64_LD3LN_WB_B_fixed: case AArch64_LD3LN_WB_B_register:
+               case AArch64_LD3LN_WB_H_fixed: case AArch64_LD3LN_WB_H_register:
+               case AArch64_LD3LN_WB_S_fixed: case AArch64_LD3LN_WB_S_register:
+               case AArch64_LD3LN_WB_D_fixed: case AArch64_LD3LN_WB_D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD3LN_WB_B_fixed: case AArch64_LD3LN_WB_B_register:
+                                               TransferBytes = 3; break;
+                                       case AArch64_LD3LN_WB_H_fixed: case AArch64_LD3LN_WB_H_register:
+                                               TransferBytes = 6; break;
+                                       case AArch64_LD3LN_WB_S_fixed: case AArch64_LD3LN_WB_S_register:
+                                               TransferBytes = 12; break;
+                                       case AArch64_LD3LN_WB_D_fixed: case AArch64_LD3LN_WB_D_register:
+                                               TransferBytes = 24; break;
+                               }
+                               IsLoad = true;
+                               NumVecs = 3;
+                               break;
+                       }
+
+               case AArch64_LD4LN_WB_B_fixed: case AArch64_LD4LN_WB_B_register:
+               case AArch64_LD4LN_WB_H_fixed: case AArch64_LD4LN_WB_H_register:
+               case AArch64_LD4LN_WB_S_fixed: case AArch64_LD4LN_WB_S_register:
+               case AArch64_LD4LN_WB_D_fixed: case AArch64_LD4LN_WB_D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_LD4LN_WB_B_fixed: case AArch64_LD4LN_WB_B_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_LD4LN_WB_H_fixed: case AArch64_LD4LN_WB_H_register:
+                                               TransferBytes = 8; break;
+                                       case AArch64_LD4LN_WB_S_fixed: case AArch64_LD4LN_WB_S_register:
+                                               TransferBytes = 16; break;
+                                       case AArch64_LD4LN_WB_D_fixed: case AArch64_LD4LN_WB_D_register:
+                                               TransferBytes = 32; break;
+                               }
+                               IsLoad = true;
+                               NumVecs = 4;
+                               break;
+                       }
+
+               case AArch64_ST1LN_WB_B_fixed: case AArch64_ST1LN_WB_B_register:
+               case AArch64_ST1LN_WB_H_fixed: case AArch64_ST1LN_WB_H_register:
+               case AArch64_ST1LN_WB_S_fixed: case AArch64_ST1LN_WB_S_register:
+               case AArch64_ST1LN_WB_D_fixed: case AArch64_ST1LN_WB_D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_ST1LN_WB_B_fixed: case AArch64_ST1LN_WB_B_register:
+                                               TransferBytes = 1; break;
+                                       case AArch64_ST1LN_WB_H_fixed: case AArch64_ST1LN_WB_H_register:
+                                               TransferBytes = 2; break;
+                                       case AArch64_ST1LN_WB_S_fixed: case AArch64_ST1LN_WB_S_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_ST1LN_WB_D_fixed: case AArch64_ST1LN_WB_D_register:
+                                               TransferBytes = 8; break;
+                               }
+                               NumVecs = 1;
+                               break;
+                       }
+
+               case AArch64_ST2LN_WB_B_fixed: case AArch64_ST2LN_WB_B_register:
+               case AArch64_ST2LN_WB_H_fixed: case AArch64_ST2LN_WB_H_register:
+               case AArch64_ST2LN_WB_S_fixed: case AArch64_ST2LN_WB_S_register:
+               case AArch64_ST2LN_WB_D_fixed: case AArch64_ST2LN_WB_D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_ST2LN_WB_B_fixed: case AArch64_ST2LN_WB_B_register:
+                                               TransferBytes = 2; break;
+                                       case AArch64_ST2LN_WB_H_fixed: case AArch64_ST2LN_WB_H_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_ST2LN_WB_S_fixed: case AArch64_ST2LN_WB_S_register:
+                                               TransferBytes = 8; break;
+                                       case AArch64_ST2LN_WB_D_fixed: case AArch64_ST2LN_WB_D_register:
+                                               TransferBytes = 16; break;
+                               }
+                               NumVecs = 2;
+                               break;
+                       }
+
+               case AArch64_ST3LN_WB_B_fixed: case AArch64_ST3LN_WB_B_register:
+               case AArch64_ST3LN_WB_H_fixed: case AArch64_ST3LN_WB_H_register:
+               case AArch64_ST3LN_WB_S_fixed: case AArch64_ST3LN_WB_S_register:
+               case AArch64_ST3LN_WB_D_fixed: case AArch64_ST3LN_WB_D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_ST3LN_WB_B_fixed: case AArch64_ST3LN_WB_B_register:
+                                               TransferBytes = 3; break;
+                                       case AArch64_ST3LN_WB_H_fixed: case AArch64_ST3LN_WB_H_register:
+                                               TransferBytes = 6; break;
+                                       case AArch64_ST3LN_WB_S_fixed: case AArch64_ST3LN_WB_S_register:
+                                               TransferBytes = 12; break;
+                                       case AArch64_ST3LN_WB_D_fixed: case AArch64_ST3LN_WB_D_register:
+                                               TransferBytes = 24; break;
+                               }
+                               NumVecs = 3;
+                               break;
+                       }
+
+               case AArch64_ST4LN_WB_B_fixed: case AArch64_ST4LN_WB_B_register:
+               case AArch64_ST4LN_WB_H_fixed: case AArch64_ST4LN_WB_H_register:
+               case AArch64_ST4LN_WB_S_fixed: case AArch64_ST4LN_WB_S_register:
+               case AArch64_ST4LN_WB_D_fixed: case AArch64_ST4LN_WB_D_register:
+                       {
+                               switch (Opc) {
+                                       case AArch64_ST4LN_WB_B_fixed: case AArch64_ST4LN_WB_B_register:
+                                               TransferBytes = 4; break;
+                                       case AArch64_ST4LN_WB_H_fixed: case AArch64_ST4LN_WB_H_register:
+                                               TransferBytes = 8; break;
+                                       case AArch64_ST4LN_WB_S_fixed: case AArch64_ST4LN_WB_S_register:
+                                               TransferBytes = 16; break;
+                                       case AArch64_ST4LN_WB_D_fixed: case AArch64_ST4LN_WB_D_register:
+                                               TransferBytes = 32; break;
+                               }
+                               NumVecs = 4;
+                               break;
+                       }
+
+               default:
+                       return MCDisassembler_Fail;
+       } // End of switch (Opc)
+
+       unsigned Rt = fieldFromInstruction(Insn, 0, 5);
+       unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+       unsigned Rm = fieldFromInstruction(Insn, 16, 5);
+
+       // Decode post-index of load duplicate lane
+       if (IsLoadDup) {
+               switch (NumVecs) {
+                       case 1:
+                               Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 2:
+                               Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 3:
+                               Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 4:
+                               Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder)
+                                       : DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
+               }
+
+               // Decode write back register, which is equal to Rn.
+               DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+               DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+
+               if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
+                       MCInst_addOperand(Inst, MCOperand_CreateImm(TransferBytes));
+               else // Decode Rm
+                       DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
+
+               return MCDisassembler_Success;
+       }
+
+       // Decode post-index of load/store lane
+       // Loads have a vector list as output.
+       if (IsLoad) {
+               switch (NumVecs) {
+                       case 1:
+                               DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 2:
+                               DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 3:
+                               DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
+                               break;
+                       case 4:
+                               DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
+               }
+       }
+
+       // Decode write back register, which is equal to Rn.
+       DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+       DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+
+       if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
+               MCInst_addOperand(Inst, MCOperand_CreateImm(TransferBytes));
+       else // Decode Rm
+               DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
+
+       // Decode the source vector list.
+       switch (NumVecs) {
+               case 1:
+                       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
+                       break;
+               case 2:
+                       DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
+                       break;
+               case 3:
+                       DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
+                       break;
+               case 4:
+                       DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
+       }
+
+       // Decode lane
+       unsigned Q = fieldFromInstruction(Insn, 30, 1);
+       unsigned S = fieldFromInstruction(Insn, 10, 3);
+       unsigned lane = 0;
+       // Calculate the number of lanes by number of vectors and transfered bytes.
+       // NumLanes = 16 bytes / bytes of each lane
+       unsigned NumLanes = 16 / (TransferBytes / NumVecs);
+       switch (NumLanes) {
+               case 16: // A vector has 16 lanes, each lane is 1 bytes.
+                       lane = (Q << 3) | S;
+                       break;
+               case 8:
+                       lane = (Q << 2) | (S >> 1);
+                       break;
+               case 4:
+                       lane = (Q << 1) | (S >> 2);
+                       break;
+               case 2:
+                       lane = Q;
+                       break;
+       }
+       MCInst_addOperand(Inst, MCOperand_CreateImm(lane));
+
+       return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSHLLInstruction(MCInst *Inst, unsigned Insn,
+               uint64_t Address,
+               void *Decoder)
+{
+       unsigned Rd = fieldFromInstruction(Insn, 0, 5);
+       unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+       unsigned size = fieldFromInstruction(Insn, 22, 2);
+       unsigned Q = fieldFromInstruction(Insn, 30, 1);
+
+       DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
+
+       if (Q)
+               DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
+       else
+               DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder);
+
+       switch (size) {
+               case 0:
+                       MCInst_addOperand(Inst, MCOperand_CreateImm(8));
+                       break;
+               case 1:
+                       MCInst_addOperand(Inst, MCOperand_CreateImm(16));
+                       break;
+               case 2:
+                       MCInst_addOperand(Inst, MCOperand_CreateImm(32));
+                       break;
+               default :
+                       return MCDisassembler_Fail;
+       }
+       return MCDisassembler_Success;
+}
+
diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h
new file mode 100644 (file)
index 0000000..65853f4
--- /dev/null
@@ -0,0 +1,18 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef __SB_AARCH64DISASSEMBLER_H
+#define __SB_AARCH64DISASSEMBLER_H
+
+#include <stdint.h>
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void AArch64_init(MCRegisterInfo *MRI);
+
+bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+               MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
new file mode 100644 (file)
index 0000000..9c4870c
--- /dev/null
@@ -0,0 +1,11767 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Assembly Writer Source Fragment                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void AArch64InstPrinter_printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+{
+  static uint32_t OpInfo[] = {
+    0U,        // PHI
+    0U,        // INLINEASM
+    0U,        // PROLOG_LABEL
+    0U,        // EH_LABEL
+    0U,        // GC_LABEL
+    0U,        // KILL
+    0U,        // EXTRACT_SUBREG
+    0U,        // INSERT_SUBREG
+    0U,        // IMPLICIT_DEF
+    0U,        // SUBREG_TO_REG
+    0U,        // COPY_TO_REGCLASS
+    2780U,     // DBG_VALUE
+    0U,        // REG_SEQUENCE
+    0U,        // COPY
+    2773U,     // BUNDLE
+    2790U,     // LIFETIME_START
+    2760U,     // LIFETIME_END
+    0U,        // STACKMAP
+    0U,        // PATCHPOINT
+    6229U,     // ABS16b
+    1074796629U,       // ABS2d
+    2149587029U,       // ABS2s
+    3224377429U,       // ABS4h
+    4200533U,  // ABS4s
+    1078990933U,       // ABS8b
+    2153781333U,       // ABS8h
+    3262130261U,       // ABSdd
+    40904813U, // ADCSwww
+    40904813U, // ADCSxxx
+    40903414U, // ADCwww
+    40903414U, // ADCxxx
+    1140855066U,       // ADDHN2vvv_16b8h
+    2218791194U,       // ADDHN2vvv_4s2d
+    3294630170U,       // ADDHN2vvv_8h4s
+    2149586505U,       // ADDHNvvv_2s2d
+    3224376905U,       // ADDHNvvv_4h4s
+    1078990409U,       // ADDHNvvv_8b8h
+    5863U,     // ADDP_16B
+    2148538087U,       // ADDP_2D
+    1075844839U,       // ADDP_2S
+    2150635239U,       // ADDP_4H
+    3225425639U,       // ADDP_4S
+    3226474215U,       // ADDP_8B
+    1080039143U,       // ADDP_8H
+    1081091815U,       // ADDPvv_D_2D
+    40904825U, // ADDSwww_asr
+    40904825U, // ADDSwww_lsl
+    40904825U, // ADDSwww_lsr
+    40904825U, // ADDSwww_sxtb
+    40904825U, // ADDSwww_sxth
+    40904825U, // ADDSwww_sxtw
+    40904825U, // ADDSwww_sxtx
+    40904825U, // ADDSwww_uxtb
+    40904825U, // ADDSwww_uxth
+    40904825U, // ADDSwww_uxtw
+    40904825U, // ADDSwww_uxtx
+    40904825U, // ADDSxxw_sxtb
+    40904825U, // ADDSxxw_sxth
+    40904825U, // ADDSxxw_sxtw
+    40904825U, // ADDSxxw_uxtb
+    40904825U, // ADDSxxw_uxth
+    40904825U, // ADDSxxw_uxtw
+    40904825U, // ADDSxxx_asr
+    40904825U, // ADDSxxx_lsl
+    40904825U, // ADDSxxx_lsr
+    40904825U, // ADDSxxx_sxtx
+    40904825U, // ADDSxxx_uxtx
+    7350616U,  // ADDV_1b16b
+    1081092440U,       // ADDV_1b8b
+    3228576088U,       // ADDV_1h4h
+    2154834264U,       // ADDV_1h8h
+    7350616U,  // ADDV_1s4s
+    40903475U, // ADDddd
+    4915U,     // ADDvvv_16B
+    2148537139U,       // ADDvvv_2D
+    1075843891U,       // ADDvvv_2S
+    2150634291U,       // ADDvvv_4H
+    3225424691U,       // ADDvvv_4S
+    3226473267U,       // ADDvvv_8B
+    1080038195U,       // ADDvvv_8H
+    40904825U, // ADDwwi_lsl0_S
+    108014267U,        // ADDwwi_lsl0_cmp
+    40903475U, // ADDwwi_lsl0_s
+    40904825U, // ADDwwi_lsl12_S
+    141568699U,        // ADDwwi_lsl12_cmp
+    40903475U, // ADDwwi_lsl12_s
+    40903475U, // ADDwww_asr
+    40903475U, // ADDwww_lsl
+    40903475U, // ADDwww_lsr
+    40903475U, // ADDwww_sxtb
+    40903475U, // ADDwww_sxth
+    40903475U, // ADDwww_sxtw
+    40903475U, // ADDwww_sxtx
+    40903475U, // ADDwww_uxtb
+    40903475U, // ADDwww_uxth
+    40903475U, // ADDwww_uxtw
+    40903475U, // ADDwww_uxtx
+    40904825U, // ADDxxi_lsl0_S
+    108014267U,        // ADDxxi_lsl0_cmp
+    40903475U, // ADDxxi_lsl0_s
+    40904825U, // ADDxxi_lsl12_S
+    141568699U,        // ADDxxi_lsl12_cmp
+    40903475U, // ADDxxi_lsl12_s
+    40903475U, // ADDxxw_sxtb
+    40903475U, // ADDxxw_sxth
+    40903475U, // ADDxxw_sxtw
+    40903475U, // ADDxxw_uxtb
+    40903475U, // ADDxxw_uxth
+    40903475U, // ADDxxw_uxtw
+    40903475U, // ADDxxx_asr
+    40903475U, // ADDxxx_lsl
+    40903475U, // ADDxxx_lsr
+    40903475U, // ADDxxx_sxtx
+    40903475U, // ADDxxx_uxtx
+    0U,        // ADJCALLSTACKDOWN
+    0U,        // ADJCALLSTACKUP
+    175122258U,        // ADRPxi
+    208676802U,        // ADRxi
+    67113850U, // AESD
+    67113908U, // AESE
+    4864U,     // AESIMC
+    4872U,     // AESMC
+    40904831U, // ANDSwwi
+    40904831U, // ANDSwww_asr
+    40904831U, // ANDSwww_lsl
+    40904831U, // ANDSwww_lsr
+    40904831U, // ANDSwww_ror
+    40904831U, // ANDSxxi
+    40904831U, // ANDSxxx_asr
+    40904831U, // ANDSxxx_lsl
+    40904831U, // ANDSxxx_lsr
+    40904831U, // ANDSxxx_ror
+    4981U,     // ANDvvv_16B
+    3226473333U,       // ANDvvv_8B
+    40903541U, // ANDwwi
+    40903541U, // ANDwww_asr
+    40903541U, // ANDwww_lsl
+    40903541U, // ANDwww_lsr
+    40903541U, // ANDwww_ror
+    40903541U, // ANDxxi
+    40903541U, // ANDxxx_asr
+    40903541U, // ANDxxx_lsl
+    40903541U, // ANDxxx_lsr
+    40903541U, // ANDxxx_ror
+    40904704U, // ASRVwww
+    40904704U, // ASRVxxx
+    40904704U, // ASRwwi
+    40904704U, // ASRxxi
+    0U,        // ATOMIC_CMP_SWAP_I16
+    0U,        // ATOMIC_CMP_SWAP_I32
+    0U,        // ATOMIC_CMP_SWAP_I64
+    0U,        // ATOMIC_CMP_SWAP_I8
+    0U,        // ATOMIC_LOAD_ADD_I16
+    0U,        // ATOMIC_LOAD_ADD_I32
+    0U,        // ATOMIC_LOAD_ADD_I64
+    0U,        // ATOMIC_LOAD_ADD_I8
+    0U,        // ATOMIC_LOAD_AND_I16
+    0U,        // ATOMIC_LOAD_AND_I32
+    0U,        // ATOMIC_LOAD_AND_I64
+    0U,        // ATOMIC_LOAD_AND_I8
+    0U,        // ATOMIC_LOAD_MAX_I16
+    0U,        // ATOMIC_LOAD_MAX_I32
+    0U,        // ATOMIC_LOAD_MAX_I64
+    0U,        // ATOMIC_LOAD_MAX_I8
+    0U,        // ATOMIC_LOAD_MIN_I16
+    0U,        // ATOMIC_LOAD_MIN_I32
+    0U,        // ATOMIC_LOAD_MIN_I64
+    0U,        // ATOMIC_LOAD_MIN_I8
+    0U,        // ATOMIC_LOAD_NAND_I16
+    0U,        // ATOMIC_LOAD_NAND_I32
+    0U,        // ATOMIC_LOAD_NAND_I64
+    0U,        // ATOMIC_LOAD_NAND_I8
+    0U,        // ATOMIC_LOAD_OR_I16
+    0U,        // ATOMIC_LOAD_OR_I32
+    0U,        // ATOMIC_LOAD_OR_I64
+    0U,        // ATOMIC_LOAD_OR_I8
+    0U,        // ATOMIC_LOAD_SUB_I16
+    0U,        // ATOMIC_LOAD_SUB_I32
+    0U,        // ATOMIC_LOAD_SUB_I64
+    0U,        // ATOMIC_LOAD_SUB_I8
+    0U,        // ATOMIC_LOAD_UMAX_I16
+    0U,        // ATOMIC_LOAD_UMAX_I32
+    0U,        // ATOMIC_LOAD_UMAX_I64
+    0U,        // ATOMIC_LOAD_UMAX_I8
+    0U,        // ATOMIC_LOAD_UMIN_I16
+    0U,        // ATOMIC_LOAD_UMIN_I32
+    0U,        // ATOMIC_LOAD_UMIN_I64
+    0U,        // ATOMIC_LOAD_UMIN_I8
+    0U,        // ATOMIC_LOAD_XOR_I16
+    0U,        // ATOMIC_LOAD_XOR_I32
+    0U,        // ATOMIC_LOAD_XOR_I64
+    0U,        // ATOMIC_LOAD_XOR_I8
+    0U,        // ATOMIC_SWAP_I16
+    0U,        // ATOMIC_SWAP_I32
+    0U,        // ATOMIC_SWAP_I64
+    0U,        // ATOMIC_SWAP_I8
+    14550U,    // ATix
+    242230450U,        // BFIwwii
+    242230450U,        // BFIxxii
+    242230800U,        // BFMwwii
+    242230800U,        // BFMxxii
+    242230681U,        // BFXILwwii
+    242230681U,        // BFXILxxii
+    40904819U, // BICSwww_asr
+    40904819U, // BICSwww_lsl
+    40904819U, // BICSwww_lsr
+    40904819U, // BICSwww_ror
+    40904819U, // BICSxxx_asr
+    40904819U, // BICSxxx_lsl
+    40904819U, // BICSxxx_lsr
+    40904819U, // BICSxxx_ror
+    270537467U,        // BICvi_lsl_2S
+    1345327867U,       // BICvi_lsl_4H
+    272634619U,        // BICvi_lsl_4S
+    1348473595U,       // BICvi_lsl_8H
+    4859U,     // BICvvv_16B
+    3226473211U,       // BICvvv_8B
+    40903419U, // BICwww_asr
+    40903419U, // BICwww_lsl
+    40903419U, // BICwww_lsr
+    40903419U, // BICwww_ror
+    40903419U, // BICxxx_asr
+    40903419U, // BICxxx_lsl
+    40903419U, // BICxxx_lsr
+    40903419U, // BICxxx_ror
+    67113932U, // BIFvvv_16B
+    3293582284U,       // BIFvvv_8B
+    67115246U, // BITvvv_16B
+    3293583598U,       // BITvvv_8B
+    8398822U,  // BLRx
+    17676U,    // BLimm
+    8398043U,  // BRKi
+    8398782U,  // BRx
+    67114444U, // BSLvvv_16B
+    3293582796U,       // BSLvvv_8B
+    23237U,    // Bcc
+    16935U,    // Bimm
+    309340826U,        // CBNZw
+    309340826U,        // CBNZx
+    309340797U,        // CBZw
+    309340797U,        // CBZx
+    40904290U, // CCMNwi
+    40904290U, // CCMNww
+    40904290U, // CCMNxi
+    40904290U, // CCMNxx
+    40904467U, // CCMPwi
+    40904467U, // CCMPww
+    40904467U, // CCMPxi
+    40904467U, // CCMPxx
+    8399443U,  // CLREXi
+    6283U,     // CLS16b
+    2149587083U,       // CLS2s
+    3224377483U,       // CLS4h
+    4200587U,  // CLS4s
+    1078990987U,       // CLS8b
+    2153781387U,       // CLS8h
+    3262130315U,       // CLSww
+    3262130315U,       // CLSxx
+    6805U,     // CLZ16b
+    2149587605U,       // CLZ2s
+    3224378005U,       // CLZ4h
+    4201109U,  // CLZ4s
+    1078991509U,       // CLZ8b
+    2153781909U,       // CLZ8h
+    3262130837U,       // CLZww
+    3262130837U,       // CLZxx
+    40904602U, // CMEQddd
+    40904602U, // CMEQddi
+    6042U,     // CMEQvvi_16B
+    2148538266U,       // CMEQvvi_2D
+    1075845018U,       // CMEQvvi_2S
+    2150635418U,       // CMEQvvi_4H
+    3225425818U,       // CMEQvvi_4S
+    3226474394U,       // CMEQvvi_8B
+    1080039322U,       // CMEQvvi_8H
+    6042U,     // CMEQvvv_16B
+    2148538266U,       // CMEQvvv_2D
+    1075845018U,       // CMEQvvv_2S
+    2150635418U,       // CMEQvvv_4H
+    3225425818U,       // CMEQvvv_4S
+    3226474394U,       // CMEQvvv_8B
+    1080039322U,       // CMEQvvv_8H
+    40903560U, // CMGEddd
+    40903560U, // CMGEddi
+    5000U,     // CMGEvvi_16B
+    2148537224U,       // CMGEvvi_2D
+    1075843976U,       // CMGEvvi_2S
+    2150634376U,       // CMGEvvi_4H
+    3225424776U,       // CMGEvvi_4S
+    3226473352U,       // CMGEvvi_8B
+    1080038280U,       // CMGEvvi_8H
+    5000U,     // CMGEvvv_16B
+    2148537224U,       // CMGEvvv_2D
+    1075843976U,       // CMGEvvv_2S
+    2150634376U,       // CMGEvvv_4H
+    3225424776U,       // CMGEvvv_4S
+    3226473352U,       // CMGEvvv_8B
+    1080038280U,       // CMGEvvv_8H
+    40904935U, // CMGTddd
+    40904935U, // CMGTddi
+    6375U,     // CMGTvvi_16B
+    2148538599U,       // CMGTvvi_2D
+    1075845351U,       // CMGTvvi_2S
+    2150635751U,       // CMGTvvi_4H
+    3225426151U,       // CMGTvvi_4S
+    3226474727U,       // CMGTvvi_8B
+    1080039655U,       // CMGTvvi_8H
+    6375U,     // CMGTvvv_16B
+    2148538599U,       // CMGTvvv_2D
+    1075845351U,       // CMGTvvv_2S
+    2150635751U,       // CMGTvvv_4H
+    3225426151U,       // CMGTvvv_4S
+    3226474727U,       // CMGTvvv_8B
+    1080039655U,       // CMGTvvv_8H
+    40903863U, // CMHIddd
+    5303U,     // CMHIvvv_16B
+    2148537527U,       // CMHIvvv_2D
+    1075844279U,       // CMHIvvv_2S
+    2150634679U,       // CMHIvvv_4H
+    3225425079U,       // CMHIvvv_4S
+    3226473655U,       // CMHIvvv_8B
+    1080038583U,       // CMHIvvv_8H
+    40904837U, // CMHSddd
+    6277U,     // CMHSvvv_16B
+    2148538501U,       // CMHSvvv_2D
+    1075845253U,       // CMHSvvv_2S
+    2150635653U,       // CMHSvvv_4H
+    3225426053U,       // CMHSvvv_4S
+    3226474629U,       // CMHSvvv_8B
+    1080039557U,       // CMHSvvv_8H
+    40903567U, // CMLEddi
+    5007U,     // CMLEvvi_16B
+    2148537231U,       // CMLEvvi_2D
+    1075843983U,       // CMLEvvi_2S
+    2150634383U,       // CMLEvvi_4H
+    3225424783U,       // CMLEvvi_4S
+    3226473359U,       // CMLEvvi_8B
+    1080038287U,       // CMLEvvi_8H
+    40904953U, // CMLTddi
+    6393U,     // CMLTvvi_16B
+    2148538617U,       // CMLTvvi_2D
+    1075845369U,       // CMLTvvi_2S
+    2150635769U,       // CMLTvvi_4H
+    3225426169U,       // CMLTvvi_4S
+    3226474745U,       // CMLTvvi_8B
+    1080039673U,       // CMLTvvi_8H
+    40904291U, // CMNww_asr
+    40904291U, // CMNww_lsl
+    40904291U, // CMNww_lsr
+    40904291U, // CMNww_sxtb
+    40904291U, // CMNww_sxth
+    40904291U, // CMNww_sxtw
+    40904291U, // CMNww_sxtx
+    40904291U, // CMNww_uxtb
+    40904291U, // CMNww_uxth
+    40904291U, // CMNww_uxtw
+    40904291U, // CMNww_uxtx
+    40904291U, // CMNxw_sxtb
+    40904291U, // CMNxw_sxth
+    40904291U, // CMNxw_sxtw
+    40904291U, // CMNxw_uxtb
+    40904291U, // CMNxw_uxth
+    40904291U, // CMNxw_uxtw
+    40904291U, // CMNxx_asr
+    40904291U, // CMNxx_lsl
+    40904291U, // CMNxx_lsr
+    40904291U, // CMNxx_sxtx
+    40904291U, // CMNxx_uxtx
+    40904468U, // CMPww_asr
+    40904468U, // CMPww_lsl
+    40904468U, // CMPww_lsr
+    40904468U, // CMPww_sxtb
+    40904468U, // CMPww_sxth
+    40904468U, // CMPww_sxtw
+    40904468U, // CMPww_sxtx
+    40904468U, // CMPww_uxtb
+    40904468U, // CMPww_uxth
+    40904468U, // CMPww_uxtw
+    40904468U, // CMPww_uxtx
+    40904468U, // CMPxw_sxtb
+    40904468U, // CMPxw_sxth
+    40904468U, // CMPxw_sxtw
+    40904468U, // CMPxw_uxtb
+    40904468U, // CMPxw_uxth
+    40904468U, // CMPxw_uxtw
+    40904468U, // CMPxx_asr
+    40904468U, // CMPxx_lsl
+    40904468U, // CMPxx_lsr
+    40904468U, // CMPxx_sxtx
+    40904468U, // CMPxx_uxtx
+    40904982U, // CMTSTddd
+    6422U,     // CMTSTvvv_16B
+    2148538646U,       // CMTSTvvv_2D
+    1075845398U,       // CMTSTvvv_2S
+    2150635798U,       // CMTSTvvv_4H
+    3225426198U,       // CMTSTvvv_4S
+    3226474774U,       // CMTSTvvv_8B
+    1080039702U,       // CMTSTvvv_8H
+    6399U,     // CNT16b
+    1078991103U,       // CNT8b
+    40903202U, // CRC32B_www
+    40903210U, // CRC32CB_www
+    40903691U, // CRC32CH_www
+    40905200U, // CRC32CW_www
+    40905290U, // CRC32CX_wwx
+    40903674U, // CRC32H_www
+    40905178U, // CRC32W_www
+    40905259U, // CRC32X_wwx
+    40904027U, // CSELwwwc
+    40904027U, // CSELxxxc
+    40903439U, // CSINCwwwc
+    40903439U, // CSINCxxxc
+    40905132U, // CSINVwwwc
+    40905132U, // CSINVxxxc
+    40903660U, // CSNEGwwwc
+    40903660U, // CSNEGxxxc
+    8396844U,  // DCPS1i
+    8397209U,  // DCPS2i
+    8397258U,  // DCPS3i
+    25335U,    // DCix
+    29235U,    // DMBi
+    2805U,     // DRPS
+    29324U,    // DSBi
+    3254785893U,       // DUP16b
+    3255834469U,       // DUP2d
+    3256883045U,       // DUP2s
+    3257931621U,       // DUP4h
+    3258980197U,       // DUP4s
+    3260028773U,       // DUP8b
+    3261077349U,       // DUP8h
+    2147489637U,       // DUPELT16b
+    3222280037U,       // DUPELT2d
+    2103141U,  // DUPELT2s
+    1076893541U,       // DUPELT4h
+    4200293U,  // DUPELT4s
+    2152732517U,       // DUPELT8b
+    1080039269U,       // DUPELT8h
+    2154833765U,       // DUPbv_B
+    3228575589U,       // DUPdv_D
+    1081091941U,       // DUPhv_H
+    7350117U,  // DUPsv_S
+    40904296U, // EONwww_asr
+    40904296U, // EONwww_lsl
+    40904296U, // EONwww_lsr
+    40904296U, // EONwww_ror
+    40904296U, // EONxxx_asr
+    40904296U, // EONxxx_lsl
+    40904296U, // EONxxx_lsr
+    40904296U, // EONxxx_ror
+    6129U,     // EORvvv_16B
+    3226474481U,       // EORvvv_8B
+    40904689U, // EORwwi
+    40904689U, // EORwww_asr
+    40904689U, // EORwww_lsl
+    40904689U, // EORwww_lsr
+    40904689U, // EORwww_ror
+    40904689U, // EORxxi
+    40904689U, // EORxxx_asr
+    40904689U, // EORxxx_lsl
+    40904689U, // EORxxx_lsr
+    40904689U, // EORxxx_ror
+    2810U,     // ERET
+    40904736U, // EXTRwwwi
+    40904736U, // EXTRxxxi
+    6435U,     // EXTvvvi_16b
+    3226474787U,       // EXTvvvi_8b
+    0U,        // F128CSEL
+    40903456U, // FABDddd
+    40903456U, // FABDsss
+    2148537120U,       // FABDvvv_2D
+    1075843872U,       // FABDvvv_2S
+    3225424672U,       // FABDvvv_4S
+    1074796628U,       // FABS2d
+    2149587028U,       // FABS2s
+    4200532U,  // FABS4s
+    3262130260U,       // FABSdd
+    3262130260U,       // FABSss
+    40903552U, // FACGEddd
+    40903552U, // FACGEsss
+    2148537216U,       // FACGEvvv_2D
+    1075843968U,       // FACGEvvv_2S
+    3225424768U,       // FACGEvvv_4S
+    40904927U, // FACGTddd
+    40904927U, // FACGTsss
+    2148538591U,       // FACGTvvv_2D
+    1075845343U,       // FACGTvvv_2S
+    3225426143U,       // FACGTvvv_4S
+    2148538086U,       // FADDP_2D
+    1075844838U,       // FADDP_2S
+    3225425638U,       // FADDP_4S
+    1081091814U,       // FADDPvv_D_2D
+    2154833638U,       // FADDPvv_S_2S
+    40903474U, // FADDddd
+    40903474U, // FADDsss
+    2148537138U,       // FADDvvv_2D
+    1075843890U,       // FADDvvv_2S
+    3225424690U,       // FADDvvv_4S
+    40903589U, // FCCMPEdd
+    40903589U, // FCCMPEss
+    40904466U, // FCCMPdd
+    40904466U, // FCCMPss
+    40904601U, // FCMEQZddi
+    40904601U, // FCMEQZssi
+    40904601U, // FCMEQddd
+    40904601U, // FCMEQsss
+    2148538265U,       // FCMEQvvi_2D
+    1075845017U,       // FCMEQvvi_2S
+    3225425817U,       // FCMEQvvi_4S
+    2148538265U,       // FCMEQvvv_2D
+    1075845017U,       // FCMEQvvv_2S
+    3225425817U,       // FCMEQvvv_4S
+    40903559U, // FCMGEZddi
+    40903559U, // FCMGEZssi
+    40903559U, // FCMGEddd
+    40903559U, // FCMGEsss
+    2148537223U,       // FCMGEvvi_2D
+    1075843975U,       // FCMGEvvi_2S
+    3225424775U,       // FCMGEvvi_4S
+    2148537223U,       // FCMGEvvv_2D
+    1075843975U,       // FCMGEvvv_2S
+    3225424775U,       // FCMGEvvv_4S
+    40904934U, // FCMGTZddi
+    40904934U, // FCMGTZssi
+    40904934U, // FCMGTddd
+    40904934U, // FCMGTsss
+    2148538598U,       // FCMGTvvi_2D
+    1075845350U,       // FCMGTvvi_2S
+    3225426150U,       // FCMGTvvi_4S
+    2148538598U,       // FCMGTvvv_2D
+    1075845350U,       // FCMGTvvv_2S
+    3225426150U,       // FCMGTvvv_4S
+    40903566U, // FCMLEZddi
+    40903566U, // FCMLEZssi
+    2148537230U,       // FCMLEvvi_2D
+    1075843982U,       // FCMLEvvi_2S
+    3225424782U,       // FCMLEvvi_4S
+    40904952U, // FCMLTZddi
+    40904952U, // FCMLTZssi
+    2148538616U,       // FCMLTvvi_2D
+    1075845368U,       // FCMLTvvi_2S
+    3225426168U,       // FCMLTvvi_4S
+    3262129945U,       // FCMPdd_quiet
+    3262129069U,       // FCMPdd_sig
+    342894361U,        // FCMPdi_quiet
+    342893485U,        // FCMPdi_sig
+    342894361U,        // FCMPsi_quiet
+    342893485U,        // FCMPsi_sig
+    3262129945U,       // FCMPss_quiet
+    3262129069U,       // FCMPss_sig
+    40904026U, // FCSELdddc
+    40904026U, // FCSELsssc
+    1074796620U,       // FCVTAS_2d
+    2149587020U,       // FCVTAS_2s
+    4200524U,  // FCVTAS_4s
+    3262130252U,       // FCVTASdd
+    3262130252U,       // FCVTASss
+    3262130252U,       // FCVTASwd
+    3262130252U,       // FCVTASws
+    3262130252U,       // FCVTASxd
+    3262130252U,       // FCVTASxs
+    1074796840U,       // FCVTAU_2d
+    2149587240U,       // FCVTAU_2s
+    4200744U,  // FCVTAU_4s
+    3262130472U,       // FCVTAUdd
+    3262130472U,       // FCVTAUss
+    3262130472U,       // FCVTAUwd
+    3262130472U,       // FCVTAUws
+    3262130472U,       // FCVTAUxd
+    3262130472U,       // FCVTAUxs
+    2148537838U,       // FCVTL2s2d
+    3225425390U,       // FCVTL4h4s
+    1052936U,  // FCVTL4s2d
+    2151682312U,       // FCVTL8h4s
+    1074796694U,       // FCVTMS_2d
+    2149587094U,       // FCVTMS_2s
+    4200598U,  // FCVTMS_4s
+    3262130326U,       // FCVTMSdd
+    3262130326U,       // FCVTMSss
+    3262130326U,       // FCVTMSwd
+    3262130326U,       // FCVTMSws
+    3262130326U,       // FCVTMSxd
+    3262130326U,       // FCVTMSxs
+    1074796856U,       // FCVTMU_2d
+    2149587256U,       // FCVTMU_2s
+    4200760U,  // FCVTMU_4s
+    3262130488U,       // FCVTMUdd
+    3262130488U,       // FCVTMUss
+    3262130488U,       // FCVTMUwd
+    3262130488U,       // FCVTMUws
+    3262130488U,       // FCVTMUxd
+    3262130488U,       // FCVTMUxs
+    1075844764U,       // FCVTN2d2s
+    1145049422U,       // FCVTN2d4s
+    3151516U,  // FCVTN4s4h
+    73404750U, // FCVTN4s8h
+    1074796707U,       // FCVTNS_2d
+    2149587107U,       // FCVTNS_2s
+    4200611U,  // FCVTNS_4s
+    3262130339U,       // FCVTNSdd
+    3262130339U,       // FCVTNSss
+    3262130339U,       // FCVTNSwd
+    3262130339U,       // FCVTNSws
+    3262130339U,       // FCVTNSxd
+    3262130339U,       // FCVTNSxs
+    1074796864U,       // FCVTNU_2d
+    2149587264U,       // FCVTNU_2s
+    4200768U,  // FCVTNU_4s
+    3262130496U,       // FCVTNUdd
+    3262130496U,       // FCVTNUss
+    3262130496U,       // FCVTNUwd
+    3262130496U,       // FCVTNUws
+    3262130496U,       // FCVTNUxd
+    3262130496U,       // FCVTNUxs
+    1074796723U,       // FCVTPS_2d
+    2149587123U,       // FCVTPS_2s
+    4200627U,  // FCVTPS_4s
+    3262130355U,       // FCVTPSdd
+    3262130355U,       // FCVTPSss
+    3262130355U,       // FCVTPSwd
+    3262130355U,       // FCVTPSws
+    3262130355U,       // FCVTPSxd
+    3262130355U,       // FCVTPSxs
+    1074796872U,       // FCVTPU_2d
+    2149587272U,       // FCVTPU_2s
+    4200776U,  // FCVTPU_4s
+    3262130504U,       // FCVTPUdd
+    3262130504U,       // FCVTPUss
+    3262130504U,       // FCVTPUwd
+    3262130504U,       // FCVTPUws
+    3262130504U,       // FCVTPUxd
+    3262130504U,       // FCVTPUxs
+    3262129879U,       // FCVTXN
+    1075844823U,       // FCVTXN2d2s
+    1145049476U,       // FCVTXN2d4s
+    1074796750U,       // FCVTZS_2d
+    2149587150U,       // FCVTZS_2s
+    4200654U,  // FCVTZS_4s
+    40904910U, // FCVTZS_Nddi
+    40904910U, // FCVTZS_Nssi
+    3262130382U,       // FCVTZSdd
+    3262130382U,       // FCVTZSss
+    3262130382U,       // FCVTZSwd
+    40904910U, // FCVTZSwdi
+    3262130382U,       // FCVTZSws
+    40904910U, // FCVTZSwsi
+    3262130382U,       // FCVTZSxd
+    40904910U, // FCVTZSxdi
+    3262130382U,       // FCVTZSxs
+    40904910U, // FCVTZSxsi
+    1074796880U,       // FCVTZU_2d
+    2149587280U,       // FCVTZU_2s
+    4200784U,  // FCVTZU_4s
+    40905040U, // FCVTZU_Nddi
+    40905040U, // FCVTZU_Nssi
+    3262130512U,       // FCVTZUdd
+    3262130512U,       // FCVTZUss
+    3262130512U,       // FCVTZUwd
+    40905040U, // FCVTZUwdi
+    3262130512U,       // FCVTZUws
+    40905040U, // FCVTZUwsi
+    3262130512U,       // FCVTZUxd
+    40905040U, // FCVTZUxdi
+    3262130512U,       // FCVTZUxs
+    40905040U, // FCVTZUxsi
+    3262130461U,       // FCVTdh
+    3262130461U,       // FCVTds
+    3262130461U,       // FCVThd
+    3262130461U,       // FCVThs
+    3262130461U,       // FCVTsd
+    3262130461U,       // FCVTsh
+    40905059U, // FDIVddd
+    40905059U, // FDIVsss
+    2148538723U,       // FDIVvvv_2D
+    1075845475U,       // FDIVvvv_2S
+    3225426275U,       // FDIVvvv_4S
+    40903510U, // FMADDdddd
+    40903510U, // FMADDssss
+    1081091880U,       // FMAXNMPvv_D_2D
+    2154833704U,       // FMAXNMPvv_S_2S
+    2148538152U,       // FMAXNMPvvv_2D
+    1075844904U,       // FMAXNMPvvv_2S
+    3225425704U,       // FMAXNMPvvv_4S
+    7350670U,  // FMAXNMV_1s4s
+    40904233U, // FMAXNMddd
+    40904233U, // FMAXNMsss
+    2148537897U,       // FMAXNMvvv_2D
+    1075844649U,       // FMAXNMvvv_2S
+    3225425449U,       // FMAXNMvvv_4S
+    1081091953U,       // FMAXPvv_D_2D
+    2154833777U,       // FMAXPvv_S_2S
+    2148538225U,       // FMAXPvvv_2D
+    1075844977U,       // FMAXPvvv_2S
+    3225425777U,       // FMAXPvvv_4S
+    7350725U,  // FMAXV_1s4s
+    40905267U, // FMAXddd
+    40905267U, // FMAXsss
+    2148538931U,       // FMAXvvv_2D
+    1075845683U,       // FMAXvvv_2S
+    3225426483U,       // FMAXvvv_4S
+    1081091871U,       // FMINNMPvv_D_2D
+    2154833695U,       // FMINNMPvv_S_2S
+    2148538143U,       // FMINNMPvvv_2D
+    1075844895U,       // FMINNMPvvv_2S
+    3225425695U,       // FMINNMPvvv_4S
+    7350661U,  // FMINNMV_1s4s
+    40904225U, // FMINNMddd
+    40904225U, // FMINNMsss
+    2148537889U,       // FMINNMvvv_2D
+    1075844641U,       // FMINNMvvv_2S
+    3225425441U,       // FMINNMvvv_4S
+    1081091895U,       // FMINPvv_D_2D
+    2154833719U,       // FMINPvv_S_2S
+    2148538167U,       // FMINPvvv_2D
+    1075844919U,       // FMINPvvv_2S
+    3225425719U,       // FMINPvvv_4S
+    7350679U,  // FMINV_1s4s
+    40904272U, // FMINddd
+    40904272U, // FMINsss
+    2148537936U,       // FMINvvv_2D
+    1075844688U,       // FMINvvv_2S
+    3225425488U,       // FMINvvv_4S
+    242229754U,        // FMLAddv_2D
+    242229754U,        // FMLAssv_4S
+    2215645690U,       // FMLAvve_2d2d
+    1142952442U,       // FMLAvve_2s4s
+    3292533242U,       // FMLAvve_4s4s
+    2215645690U,       // FMLAvvv_2D
+    1142952442U,       // FMLAvvv_2S
+    3292533242U,       // FMLAvvv_4S
+    242231440U,        // FMLSddv_2D
+    242231440U,        // FMLSssv_4S
+    2215647376U,       // FMLSvve_2d2d
+    1142954128U,       // FMLSvve_2s4s
+    3292534928U,       // FMLSvve_4s4s
+    2215647376U,       // FMLSvvv_2D
+    1142954128U,       // FMLSvvv_2S
+    3292534928U,       // FMLSvvv_4S
+    3262130611U,       // FMOVdd
+    376449459U,        // FMOVdi
+    3262130611U,       // FMOVdx
+    376449459U,        // FMOVsi
+    3262130611U,       // FMOVss
+    3262130611U,       // FMOVsw
+    370153907U,        // FMOVvi_2D
+    371202483U,        // FMOVvi_2S
+    373299635U,        // FMOVvi_4S
+    412096947U,        // FMOVvx
+    3262130611U,       // FMOVws
+    3262130611U,       // FMOVxd
+    3228576179U,       // FMOVxv
+    40903373U, // FMSUBdddd
+    40903373U, // FMSUBssss
+    40905318U, // FMULXddd
+    40905318U, // FMULXddv_2D
+    40905318U, // FMULXsss
+    40905318U, // FMULXssv_4S
+    2148538982U,       // FMULXve_2d2d
+    1075845734U,       // FMULXve_2s4s
+    3225426534U,       // FMULXve_4s4s
+    2148538982U,       // FMULXvvv_2D
+    1075845734U,       // FMULXvvv_2S
+    3225426534U,       // FMULXvvv_4S
+    40904181U, // FMULddd
+    40904181U, // FMULddv_2D
+    40904181U, // FMULsss
+    40904181U, // FMULssv_4S
+    2148537845U,       // FMULve_2d2d
+    1075844597U,       // FMULve_2s4s
+    3225425397U,       // FMULve_4s4s
+    2148537845U,       // FMULvvv_2D
+    1075844597U,       // FMULvvv_2S
+    3225425397U,       // FMULvvv_4S
+    1074795487U,       // FNEG2d
+    2149585887U,       // FNEG2s
+    4199391U,  // FNEG4s
+    3262129119U,       // FNEGdd
+    3262129119U,       // FNEGss
+    40903517U, // FNMADDdddd
+    40903517U, // FNMADDssss
+    40903380U, // FNMSUBdddd
+    40903380U, // FNMSUBssss
+    40904187U, // FNMULddd
+    40904187U, // FNMULsss
+    1074795413U,       // FRECPE_2d
+    2149585813U,       // FRECPE_2s
+    4199317U,  // FRECPE_4s
+    3262129045U,       // FRECPEdd
+    3262129045U,       // FRECPEss
+    40904875U, // FRECPSddd
+    40904875U, // FRECPSsss
+    2148538539U,       // FRECPSvvv_2D
+    1075845291U,       // FRECPSvvv_2S
+    3225426091U,       // FRECPSvvv_4S
+    3262130797U,       // FRECPXdd
+    3262130797U,       // FRECPXss
+    1074795034U,       // FRINTA_2d
+    2149585434U,       // FRINTA_2s
+    4198938U,  // FRINTA_4s
+    3262128666U,       // FRINTAdd
+    3262128666U,       // FRINTAss
+    1074795725U,       // FRINTI_2d
+    2149586125U,       // FRINTI_2s
+    4199629U,  // FRINTI_4s
+    3262129357U,       // FRINTIdd
+    3262129357U,       // FRINTIss
+    1074796081U,       // FRINTM_2d
+    2149586481U,       // FRINTM_2s
+    4199985U,  // FRINTM_4s
+    3262129713U,       // FRINTMdd
+    3262129713U,       // FRINTMss
+    1074796180U,       // FRINTN_2d
+    2149586580U,       // FRINTN_2s
+    4200084U,  // FRINTN_4s
+    3262129812U,       // FRINTNdd
+    3262129812U,       // FRINTNss
+    1074796376U,       // FRINTP_2d
+    2149586776U,       // FRINTP_2s
+    4200280U,  // FRINTP_4s
+    3262130008U,       // FRINTPdd
+    3262130008U,       // FRINTPss
+    1074797173U,       // FRINTX_2d
+    2149587573U,       // FRINTX_2s
+    4201077U,  // FRINTX_4s
+    3262130805U,       // FRINTXdd
+    3262130805U,       // FRINTXss
+    1074797222U,       // FRINTZ_2d
+    2149587622U,       // FRINTZ_2s
+    4201126U,  // FRINTZ_4s
+    3262130854U,       // FRINTZdd
+    3262130854U,       // FRINTZss
+    1074795450U,       // FRSQRTE_2d
+    2149585850U,       // FRSQRTE_2s
+    4199354U,  // FRSQRTE_4s
+    3262129082U,       // FRSQRTEdd
+    3262129082U,       // FRSQRTEss
+    40904896U, // FRSQRTSddd
+    40904896U, // FRSQRTSsss
+    2148538560U,       // FRSQRTSvvv_2D
+    1075845312U,       // FRSQRTSvvv_2S
+    3225426112U,       // FRSQRTSvvv_4S
+    1074796815U,       // FSQRT_2d
+    2149587215U,       // FSQRT_2s
+    4200719U,  // FSQRT_4s
+    3262130447U,       // FSQRTdd
+    3262130447U,       // FSQRTss
+    40903353U, // FSUBddd
+    40903353U, // FSUBsss
+    2148537017U,       // FSUBvvv_2D
+    1075843769U,       // FSUBvvv_2S
+    3225424569U,       // FSUBvvv_4S
+    8399108U,  // HINTi
+    8399091U,  // HLTi
+    8397590U,  // HVCi
+    8422140U,  // ICi
+    3262153468U,       // ICix
+    2225084574U,       // INSELb
+    2593134750U,       // INSELd
+    1152391326U,       // INSELh
+    79698078U, // INSELs
+    3466598558U,       // INSbw
+    3666876574U,       // INSdx
+    3467647134U,       // INShw
+    3468695710U,       // INSsw
+    37521U,    // ISBi
+    13672469U, // LD1LN_B
+    13676565U, // LD1LN_D
+    13680661U, // LD1LN_H
+    13684757U, // LD1LN_S
+    14721045U, // LD1LN_WB_B_fixed
+    14721045U, // LD1LN_WB_B_register
+    14725141U, // LD1LN_WB_D_fixed
+    14725141U, // LD1LN_WB_D_register
+    14729237U, // LD1LN_WB_H_fixed
+    14729237U, // LD1LN_WB_H_register
+    14733333U, // LD1LN_WB_S_fixed
+    14733333U, // LD1LN_WB_S_register
+    15787936U, // LD1R_16B
+    15792032U, // LD1R_1D
+    15796128U, // LD1R_2D
+    15800224U, // LD1R_2S
+    15804320U, // LD1R_4H
+    15808416U, // LD1R_4S
+    15812512U, // LD1R_8B
+    15816608U, // LD1R_8H
+    16836512U, // LD1R_WB_16B_fixed
+    16836512U, // LD1R_WB_16B_register
+    16840608U, // LD1R_WB_1D_fixed
+    16840608U, // LD1R_WB_1D_register
+    16844704U, // LD1R_WB_2D_fixed
+    16844704U, // LD1R_WB_2D_register
+    16848800U, // LD1R_WB_2S_fixed
+    16848800U, // LD1R_WB_2S_register
+    16852896U, // LD1R_WB_4H_fixed
+    16852896U, // LD1R_WB_4H_register
+    16856992U, // LD1R_WB_4S_fixed
+    16856992U, // LD1R_WB_4S_register
+    16861088U, // LD1R_WB_8B_fixed
+    16861088U, // LD1R_WB_8B_register
+    16865184U, // LD1R_WB_8H_fixed
+    16865184U, // LD1R_WB_8H_register
+    16834581U, // LD1WB_16B_fixed
+    16834581U, // LD1WB_16B_register
+    16838677U, // LD1WB_1D_fixed
+    16838677U, // LD1WB_1D_register
+    16842773U, // LD1WB_2D_fixed
+    16842773U, // LD1WB_2D_register
+    16846869U, // LD1WB_2S_fixed
+    16846869U, // LD1WB_2S_register
+    16850965U, // LD1WB_4H_fixed
+    16850965U, // LD1WB_4H_register
+    16855061U, // LD1WB_4S_fixed
+    16855061U, // LD1WB_4S_register
+    16859157U, // LD1WB_8B_fixed
+    16859157U, // LD1WB_8B_register
+    16863253U, // LD1WB_8H_fixed
+    16863253U, // LD1WB_8H_register
+    15786005U, // LD1_16B
+    15790101U, // LD1_1D
+    15794197U, // LD1_2D
+    15798293U, // LD1_2S
+    15802389U, // LD1_4H
+    15806485U, // LD1_4S
+    15810581U, // LD1_8B
+    15814677U, // LD1_8H
+    16867349U, // LD1x2WB_16B_fixed
+    16867349U, // LD1x2WB_16B_register
+    16871445U, // LD1x2WB_1D_fixed
+    16871445U, // LD1x2WB_1D_register
+    16875541U, // LD1x2WB_2D_fixed
+    16875541U, // LD1x2WB_2D_register
+    16879637U, // LD1x2WB_2S_fixed
+    16879637U, // LD1x2WB_2S_register
+    16883733U, // LD1x2WB_4H_fixed
+    16883733U, // LD1x2WB_4H_register
+    16887829U, // LD1x2WB_4S_fixed
+    16887829U, // LD1x2WB_4S_register
+    16891925U, // LD1x2WB_8B_fixed
+    16891925U, // LD1x2WB_8B_register
+    16896021U, // LD1x2WB_8H_fixed
+    16896021U, // LD1x2WB_8H_register
+    15818773U, // LD1x2_16B
+    15822869U, // LD1x2_1D
+    15826965U, // LD1x2_2D
+    15831061U, // LD1x2_2S
+    15835157U, // LD1x2_4H
+    15839253U, // LD1x2_4S
+    15843349U, // LD1x2_8B
+    15847445U, // LD1x2_8H
+    16900117U, // LD1x3WB_16B_fixed
+    16900117U, // LD1x3WB_16B_register
+    16904213U, // LD1x3WB_1D_fixed
+    16904213U, // LD1x3WB_1D_register
+    16908309U, // LD1x3WB_2D_fixed
+    16908309U, // LD1x3WB_2D_register
+    16912405U, // LD1x3WB_2S_fixed
+    16912405U, // LD1x3WB_2S_register
+    16916501U, // LD1x3WB_4H_fixed
+    16916501U, // LD1x3WB_4H_register
+    16920597U, // LD1x3WB_4S_fixed
+    16920597U, // LD1x3WB_4S_register
+    16924693U, // LD1x3WB_8B_fixed
+    16924693U, // LD1x3WB_8B_register
+    16928789U, // LD1x3WB_8H_fixed
+    16928789U, // LD1x3WB_8H_register
+    15851541U, // LD1x3_16B
+    15855637U, // LD1x3_1D
+    15859733U, // LD1x3_2D
+    15863829U, // LD1x3_2S
+    15867925U, // LD1x3_4H
+    15872021U, // LD1x3_4S
+    15876117U, // LD1x3_8B
+    15880213U, // LD1x3_8H
+    16932885U, // LD1x4WB_16B_fixed
+    16932885U, // LD1x4WB_16B_register
+    16936981U, // LD1x4WB_1D_fixed
+    16936981U, // LD1x4WB_1D_register
+    16941077U, // LD1x4WB_2D_fixed
+    16941077U, // LD1x4WB_2D_register
+    16945173U, // LD1x4WB_2S_fixed
+    16945173U, // LD1x4WB_2S_register
+    16949269U, // LD1x4WB_4H_fixed
+    16949269U, // LD1x4WB_4H_register
+    16953365U, // LD1x4WB_4S_fixed
+    16953365U, // LD1x4WB_4S_register
+    16957461U, // LD1x4WB_8B_fixed
+    16957461U, // LD1x4WB_8B_register
+    16961557U, // LD1x4WB_8H_fixed
+    16961557U, // LD1x4WB_8H_register
+    15884309U, // LD1x4_16B
+    15888405U, // LD1x4_1D
+    15892501U, // LD1x4_2D
+    15896597U, // LD1x4_2S
+    15900693U, // LD1x4_4H
+    15904789U, // LD1x4_4S
+    15908885U, // LD1x4_8B
+    15912981U, // LD1x4_8H
+    13819987U, // LD2LN_B
+    13824083U, // LD2LN_D
+    13828179U, // LD2LN_H
+    13832275U, // LD2LN_S
+    14868563U, // LD2LN_WB_B_fixed
+    14868563U, // LD2LN_WB_B_register
+    14872659U, // LD2LN_WB_D_fixed
+    14872659U, // LD2LN_WB_D_register
+    14876755U, // LD2LN_WB_H_fixed
+    14876755U, // LD2LN_WB_H_register
+    14880851U, // LD2LN_WB_S_fixed
+    14880851U, // LD2LN_WB_S_register
+    15820710U, // LD2R_16B
+    15824806U, // LD2R_1D
+    15828902U, // LD2R_2D
+    15832998U, // LD2R_2S
+    15837094U, // LD2R_4H
+    15841190U, // LD2R_4S
+    15845286U, // LD2R_8B
+    15849382U, // LD2R_8H
+    16869286U, // LD2R_WB_16B_fixed
+    16869286U, // LD2R_WB_16B_register
+    16873382U, // LD2R_WB_1D_fixed
+    16873382U, // LD2R_WB_1D_register
+    16877478U, // LD2R_WB_2D_fixed
+    16877478U, // LD2R_WB_2D_register
+    16881574U, // LD2R_WB_2S_fixed
+    16881574U, // LD2R_WB_2S_register
+    16885670U, // LD2R_WB_4H_fixed
+    16885670U, // LD2R_WB_4H_register
+    16889766U, // LD2R_WB_4S_fixed
+    16889766U, // LD2R_WB_4S_register
+    16893862U, // LD2R_WB_8B_fixed
+    16893862U, // LD2R_WB_8B_register
+    16897958U, // LD2R_WB_8H_fixed
+    16897958U, // LD2R_WB_8H_register
+    16867411U, // LD2WB_16B_fixed
+    16867411U, // LD2WB_16B_register
+    16875603U, // LD2WB_2D_fixed
+    16875603U, // LD2WB_2D_register
+    16879699U, // LD2WB_2S_fixed
+    16879699U, // LD2WB_2S_register
+    16883795U, // LD2WB_4H_fixed
+    16883795U, // LD2WB_4H_register
+    16887891U, // LD2WB_4S_fixed
+    16887891U, // LD2WB_4S_register
+    16891987U, // LD2WB_8B_fixed
+    16891987U, // LD2WB_8B_register
+    16896083U, // LD2WB_8H_fixed
+    16896083U, // LD2WB_8H_register
+    15818835U, // LD2_16B
+    15827027U, // LD2_2D
+    15831123U, // LD2_2S
+    15835219U, // LD2_4H
+    15839315U, // LD2_4S
+    15843411U, // LD2_8B
+    15847507U, // LD2_8H
+    13836741U, // LD3LN_B
+    13840837U, // LD3LN_D
+    13844933U, // LD3LN_H
+    13849029U, // LD3LN_S
+    14885317U, // LD3LN_WB_B_fixed
+    14885317U, // LD3LN_WB_B_register
+    14889413U, // LD3LN_WB_D_fixed
+    14889413U, // LD3LN_WB_D_register
+    14893509U, // LD3LN_WB_H_fixed
+    14893509U, // LD3LN_WB_H_register
+    14897605U, // LD3LN_WB_S_fixed
+    14897605U, // LD3LN_WB_S_register
+    15853484U, // LD3R_16B
+    15857580U, // LD3R_1D
+    15861676U, // LD3R_2D
+    15865772U, // LD3R_2S
+    15869868U, // LD3R_4H
+    15873964U, // LD3R_4S
+    15878060U, // LD3R_8B
+    15882156U, // LD3R_8H
+    16902060U, // LD3R_WB_16B_fixed
+    16902060U, // LD3R_WB_16B_register
+    16906156U, // LD3R_WB_1D_fixed
+    16906156U, // LD3R_WB_1D_register
+    16910252U, // LD3R_WB_2D_fixed
+    16910252U, // LD3R_WB_2D_register
+    16914348U, // LD3R_WB_2S_fixed
+    16914348U, // LD3R_WB_2S_register
+    16918444U, // LD3R_WB_4H_fixed
+    16918444U, // LD3R_WB_4H_register
+    16922540U, // LD3R_WB_4S_fixed
+    16922540U, // LD3R_WB_4S_register
+    16926636U, // LD3R_WB_8B_fixed
+    16926636U, // LD3R_WB_8B_register
+    16930732U, // LD3R_WB_8H_fixed
+    16930732U, // LD3R_WB_8H_register
+    16900549U, // LD3WB_16B_fixed
+    16900549U, // LD3WB_16B_register
+    16908741U, // LD3WB_2D_fixed
+    16908741U, // LD3WB_2D_register
+    16912837U, // LD3WB_2S_fixed
+    16912837U, // LD3WB_2S_register
+    16916933U, // LD3WB_4H_fixed
+    16916933U, // LD3WB_4H_register
+    16921029U, // LD3WB_4S_fixed
+    16921029U, // LD3WB_4S_register
+    16925125U, // LD3WB_8B_fixed
+    16925125U, // LD3WB_8B_register
+    16929221U, // LD3WB_8H_fixed
+    16929221U, // LD3WB_8H_register
+    15851973U, // LD3_16B
+    15860165U, // LD3_2D
+    15864261U, // LD3_2S
+    15868357U, // LD3_4H
+    15872453U, // LD3_4S
+    15876549U, // LD3_8B
+    15880645U, // LD3_8H
+    13853149U, // LD4LN_B
+    13857245U, // LD4LN_D
+    13861341U, // LD4LN_H
+    13865437U, // LD4LN_S
+    14901725U, // LD4LN_WB_B_fixed
+    14901725U, // LD4LN_WB_B_register
+    14905821U, // LD4LN_WB_D_fixed
+    14905821U, // LD4LN_WB_D_register
+    14909917U, // LD4LN_WB_H_fixed
+    14909917U, // LD4LN_WB_H_register
+    14914013U, // LD4LN_WB_S_fixed
+    14914013U, // LD4LN_WB_S_register
+    15886258U, // LD4R_16B
+    15890354U, // LD4R_1D
+    15894450U, // LD4R_2D
+    15898546U, // LD4R_2S
+    15902642U, // LD4R_4H
+    15906738U, // LD4R_4S
+    15910834U, // LD4R_8B
+    15914930U, // LD4R_8H
+    16934834U, // LD4R_WB_16B_fixed
+    16934834U, // LD4R_WB_16B_register
+    16938930U, // LD4R_WB_1D_fixed
+    16938930U, // LD4R_WB_1D_register
+    16943026U, // LD4R_WB_2D_fixed
+    16943026U, // LD4R_WB_2D_register
+    16947122U, // LD4R_WB_2S_fixed
+    16947122U, // LD4R_WB_2S_register
+    16951218U, // LD4R_WB_4H_fixed
+    16951218U, // LD4R_WB_4H_register
+    16955314U, // LD4R_WB_4S_fixed
+    16955314U, // LD4R_WB_4S_register
+    16959410U, // LD4R_WB_8B_fixed
+    16959410U, // LD4R_WB_8B_register
+    16963506U, // LD4R_WB_8H_fixed
+    16963506U, // LD4R_WB_8H_register
+    16933341U, // LD4WB_16B_fixed
+    16933341U, // LD4WB_16B_register
+    16941533U, // LD4WB_2D_fixed
+    16941533U, // LD4WB_2D_register
+    16945629U, // LD4WB_2S_fixed
+    16945629U, // LD4WB_2S_register
+    16949725U, // LD4WB_4H_fixed
+    16949725U, // LD4WB_4H_register
+    16953821U, // LD4WB_4S_fixed
+    16953821U, // LD4WB_4S_register
+    16957917U, // LD4WB_8B_fixed
+    16957917U, // LD4WB_8B_register
+    16962013U, // LD4WB_8H_fixed
+    16962013U, // LD4WB_8H_register
+    15884765U, // LD4_16B
+    15892957U, // LD4_2D
+    15897053U, // LD4_2S
+    15901149U, // LD4_4H
+    15905245U, // LD4_4S
+    15909341U, // LD4_8B
+    15913437U, // LD4_8H
+    51388984U, // LDAR_byte
+    51390392U, // LDAR_dword
+    51389493U, // LDAR_hword
+    51390392U, // LDAR_word
+    1114646378U,       // LDAXP_dword
+    1114646378U,       // LDAXP_word
+    51389038U, // LDAXR_byte
+    51390514U, // LDAXR_dword
+    51389547U, // LDAXR_hword
+    51390514U, // LDAXR_word
+    1114647047U,       // LDPSWx
+    1114647047U,       // LDPSWx_PostInd
+    1114647047U,       // LDPSWx_PreInd
+    51389078U, // LDRSBw
+    2400199318U,       // LDRSBw_PostInd
+    252715670U,        // LDRSBw_PreInd
+    51389093U, // LDRSBw_U
+    51389078U, // LDRSBw_Wm_RegOffset
+    51389078U, // LDRSBw_Xm_RegOffset
+    51389078U, // LDRSBx
+    2400199318U,       // LDRSBx_PostInd
+    252715670U,        // LDRSBx_PreInd
+    51389093U, // LDRSBx_U
+    51389078U, // LDRSBx_Wm_RegOffset
+    51389078U, // LDRSBx_Xm_RegOffset
+    51389577U, // LDRSHw
+    2400199817U,       // LDRSHw_PostInd
+    252716169U,        // LDRSHw_PreInd
+    51389592U, // LDRSHw_U
+    51389577U, // LDRSHw_Wm_RegOffset
+    51389577U, // LDRSHw_Xm_RegOffset
+    51389577U, // LDRSHx
+    2400199817U,       // LDRSHx_PostInd
+    252716169U,        // LDRSHx_PreInd
+    51389592U, // LDRSHx_U
+    51389577U, // LDRSHx_Wm_RegOffset
+    51389577U, // LDRSHx_Xm_RegOffset
+    51390990U, // LDRSWx
+    2400201230U,       // LDRSWx_PostInd
+    252717582U,        // LDRSWx_PreInd
+    51390990U, // LDRSWx_Wm_RegOffset
+    51390990U, // LDRSWx_Xm_RegOffset
+    309340686U,        // LDRSWx_lit
+    309340103U,        // LDRd_lit
+    309340103U,        // LDRq_lit
+    309340103U,        // LDRs_lit
+    309340103U,        // LDRw_lit
+    309340103U,        // LDRx_lit
+    51389085U, // LDTRSBw
+    51389085U, // LDTRSBx
+    51389584U, // LDTRSHw
+    51389584U, // LDTRSHx
+    51390997U, // LDTRSWx
+    51391005U, // LDURSWx
+    1114646406U,       // LDXP_dword
+    1114646406U,       // LDXP_word
+    51389046U, // LDXR_byte
+    51390521U, // LDXR_dword
+    51389555U, // LDXR_hword
+    51390521U, // LDXR_word
+    51389500U, // LS16_LDR
+    51389533U, // LS16_LDUR
+    2400199740U,       // LS16_PostInd_LDR
+    2400429136U,       // LS16_PostInd_STR
+    252716092U,        // LS16_PreInd_LDR
+    252945488U,        // LS16_PreInd_STR
+    51389520U, // LS16_STR
+    51389540U, // LS16_STUR
+    51389513U, // LS16_UnPriv_LDR
+    51389526U, // LS16_UnPriv_STR
+    51389500U, // LS16_Wm_RegOffset_LDR
+    51389520U, // LS16_Wm_RegOffset_STR
+    51389500U, // LS16_Xm_RegOffset_LDR
+    51389520U, // LS16_Xm_RegOffset_STR
+    51390407U, // LS32_LDR
+    51390502U, // LS32_LDUR
+    2400200647U,       // LS32_PostInd_LDR
+    2400430101U,       // LS32_PostInd_STR
+    252716999U,        // LS32_PreInd_LDR
+    252946453U,        // LS32_PreInd_STR
+    51390485U, // LS32_STR
+    51390508U, // LS32_STUR
+    51390479U, // LS32_UnPriv_LDR
+    51390490U, // LS32_UnPriv_STR
+    51390407U, // LS32_Wm_RegOffset_LDR
+    51390485U, // LS32_Wm_RegOffset_STR
+    51390407U, // LS32_Xm_RegOffset_LDR
+    51390485U, // LS32_Xm_RegOffset_STR
+    51390407U, // LS64_LDR
+    51390502U, // LS64_LDUR
+    2400200647U,       // LS64_PostInd_LDR
+    2400430101U,       // LS64_PostInd_STR
+    252716999U,        // LS64_PreInd_LDR
+    252946453U,        // LS64_PreInd_STR
+    51390485U, // LS64_STR
+    51390508U, // LS64_STUR
+    51390479U, // LS64_UnPriv_LDR
+    51390490U, // LS64_UnPriv_STR
+    51390407U, // LS64_Wm_RegOffset_LDR
+    51390485U, // LS64_Wm_RegOffset_STR
+    51390407U, // LS64_Xm_RegOffset_LDR
+    51390485U, // LS64_Xm_RegOffset_STR
+    51388991U, // LS8_LDR
+    51389024U, // LS8_LDUR
+    2400199231U,       // LS8_PostInd_LDR
+    2400428627U,       // LS8_PostInd_STR
+    252715583U,        // LS8_PreInd_LDR
+    252944979U,        // LS8_PreInd_STR
+    51389011U, // LS8_STR
+    51389031U, // LS8_STUR
+    51389004U, // LS8_UnPriv_LDR
+    51389017U, // LS8_UnPriv_STR
+    51388991U, // LS8_Wm_RegOffset_LDR
+    51389011U, // LS8_Wm_RegOffset_STR
+    51388991U, // LS8_Xm_RegOffset_LDR
+    51389011U, // LS8_Xm_RegOffset_STR
+    51390407U, // LSFP128_LDR
+    51390502U, // LSFP128_LDUR
+    2400200647U,       // LSFP128_PostInd_LDR
+    2400430101U,       // LSFP128_PostInd_STR
+    252716999U,        // LSFP128_PreInd_LDR
+    252946453U,        // LSFP128_PreInd_STR
+    51390485U, // LSFP128_STR
+    51390508U, // LSFP128_STUR
+    51390407U, // LSFP128_Wm_RegOffset_LDR
+    51390485U, // LSFP128_Wm_RegOffset_STR
+    51390407U, // LSFP128_Xm_RegOffset_LDR
+    51390485U, // LSFP128_Xm_RegOffset_STR
+    51390407U, // LSFP16_LDR
+    51390502U, // LSFP16_LDUR
+    2400200647U,       // LSFP16_PostInd_LDR
+    2400430101U,       // LSFP16_PostInd_STR
+    252716999U,        // LSFP16_PreInd_LDR
+    252946453U,        // LSFP16_PreInd_STR
+    51390485U, // LSFP16_STR
+    51390508U, // LSFP16_STUR
+    51390407U, // LSFP16_Wm_RegOffset_LDR
+    51390485U, // LSFP16_Wm_RegOffset_STR
+    51390407U, // LSFP16_Xm_RegOffset_LDR
+    51390485U, // LSFP16_Xm_RegOffset_STR
+    51390407U, // LSFP32_LDR
+    51390502U, // LSFP32_LDUR
+    2400200647U,       // LSFP32_PostInd_LDR
+    2400430101U,       // LSFP32_PostInd_STR
+    252716999U,        // LSFP32_PreInd_LDR
+    252946453U,        // LSFP32_PreInd_STR
+    51390485U, // LSFP32_STR
+    51390508U, // LSFP32_STUR
+    51390407U, // LSFP32_Wm_RegOffset_LDR
+    51390485U, // LSFP32_Wm_RegOffset_STR
+    51390407U, // LSFP32_Xm_RegOffset_LDR
+    51390485U, // LSFP32_Xm_RegOffset_STR
+    51390407U, // LSFP64_LDR
+    51390502U, // LSFP64_LDUR
+    2400200647U,       // LSFP64_PostInd_LDR
+    2400430101U,       // LSFP64_PostInd_STR
+    252716999U,        // LSFP64_PreInd_LDR
+    252946453U,        // LSFP64_PreInd_STR
+    51390485U, // LSFP64_STR
+    51390508U, // LSFP64_STUR
+    51390407U, // LSFP64_Wm_RegOffset_LDR
+    51390485U, // LSFP64_Wm_RegOffset_STR
+    51390407U, // LSFP64_Xm_RegOffset_LDR
+    51390485U, // LSFP64_Xm_RegOffset_STR
+    51390407U, // LSFP8_LDR
+    51390502U, // LSFP8_LDUR
+    2400200647U,       // LSFP8_PostInd_LDR
+    2400430101U,       // LSFP8_PostInd_STR
+    252716999U,        // LSFP8_PreInd_LDR
+    252946453U,        // LSFP8_PreInd_STR
+    51390485U, // LSFP8_STR
+    51390508U, // LSFP8_STUR
+    51390407U, // LSFP8_Wm_RegOffset_LDR
+    51390485U, // LSFP8_Wm_RegOffset_STR
+    51390407U, // LSFP8_Xm_RegOffset_LDR
+    51390485U, // LSFP8_Xm_RegOffset_STR
+    1114646253U,       // LSFPPair128_LDR
+    1114646321U,       // LSFPPair128_NonTemp_LDR
+    1114646348U,       // LSFPPair128_NonTemp_STR
+    1114646253U,       // LSFPPair128_PostInd_LDR
+    1316202336U,       // LSFPPair128_PostInd_STR
+    1114646253U,       // LSFPPair128_PreInd_LDR
+    1316202336U,       // LSFPPair128_PreInd_STR
+    1114646368U,       // LSFPPair128_STR
+    1114646253U,       // LSFPPair32_LDR
+    1114646321U,       // LSFPPair32_NonTemp_LDR
+    1114646348U,       // LSFPPair32_NonTemp_STR
+    1114646253U,       // LSFPPair32_PostInd_LDR
+    1316202336U,       // LSFPPair32_PostInd_STR
+    1114646253U,       // LSFPPair32_PreInd_LDR
+    1316202336U,       // LSFPPair32_PreInd_STR
+    1114646368U,       // LSFPPair32_STR
+    1114646253U,       // LSFPPair64_LDR
+    1114646321U,       // LSFPPair64_NonTemp_LDR
+    1114646348U,       // LSFPPair64_NonTemp_STR
+    1114646253U,       // LSFPPair64_PostInd_LDR
+    1316202336U,       // LSFPPair64_PostInd_STR
+    1114646253U,       // LSFPPair64_PreInd_LDR
+    1316202336U,       // LSFPPair64_PreInd_STR
+    1114646368U,       // LSFPPair64_STR
+    40904149U, // LSLVwww
+    40904149U, // LSLVxxx
+    40904149U, // LSLwwi
+    40904149U, // LSLxxi
+    1114646253U,       // LSPair32_LDR
+    1114646321U,       // LSPair32_NonTemp_LDR
+    1114646348U,       // LSPair32_NonTemp_STR
+    1114646253U,       // LSPair32_PostInd_LDR
+    1316202336U,       // LSPair32_PostInd_STR
+    1114646253U,       // LSPair32_PreInd_LDR
+    1316202336U,       // LSPair32_PreInd_STR
+    1114646368U,       // LSPair32_STR
+    1114646253U,       // LSPair64_LDR
+    1114646321U,       // LSPair64_NonTemp_LDR
+    1114646348U,       // LSPair64_NonTemp_STR
+    1114646253U,       // LSPair64_PostInd_LDR
+    1316202336U,       // LSPair64_PostInd_STR
+    1114646253U,       // LSPair64_PreInd_LDR
+    1316202336U,       // LSPair64_PreInd_STR
+    1114646368U,       // LSPair64_STR
+    40904709U, // LSRVwww
+    40904709U, // LSRVxxx
+    40904709U, // LSRwwi
+    40904709U, // LSRxxi
+    40903511U, // MADDwwww
+    40903511U, // MADDxxxx
+    1142952443U,       // MLAvve_2s4s
+    2217742843U,       // MLAvve_4h8h
+    3292533243U,       // MLAvve_4s4s
+    1147146747U,       // MLAvve_8h8h
+    67113467U, // MLAvvv_16B
+    1142952443U,       // MLAvvv_2S
+    2217742843U,       // MLAvvv_4H
+    3292533243U,       // MLAvvv_4S
+    3293581819U,       // MLAvvv_8B
+    1147146747U,       // MLAvvv_8H
+    1142954129U,       // MLSvve_2s4s
+    2217744529U,       // MLSvve_4h8h
+    3292534929U,       // MLSvve_4s4s
+    1147148433U,       // MLSvve_8h8h
+    67115153U, // MLSvvv_16B
+    1142954129U,       // MLSvvv_2S
+    2217744529U,       // MLSvvv_4H
+    3292534929U,       // MLSvvv_4S
+    3293583505U,       // MLSvvv_8B
+    1147148433U,       // MLSvvv_8H
+    477113012U,        // MOVIdi
+    3724547285U,       // MOVIvi_16B
+    470817460U,        // MOVIvi_2D
+    3729790165U,       // MOVIvi_8B
+    3726644437U,       // MOVIvi_lsl_2S
+    506467541U,        // MOVIvi_lsl_4H
+    3728741589U,       // MOVIvi_lsl_4S
+    509613269U,        // MOVIvi_lsl_8H
+    1579160789U,       // MOVIvi_msl_2S
+    1581257941U,       // MOVIvi_msl_4S
+    544220384U,        // MOVKwii
+    544220384U,        // MOVKxii
+    577775313U,        // MOVNwii
+    577775313U,        // MOVNxii
+    577776302U,        // MOVZwii
+    577776302U,        // MOVZxii
+    611330235U,        // MRSxi
+    243722U,   // MSRii
+    247818U,   // MSRix
+    40903374U, // MSUBwwww
+    40903374U, // MSUBxxxx
+    1075844598U,       // MULve_2s4s
+    2150634998U,       // MULve_4h8h
+    3225425398U,       // MULve_4s4s
+    1080038902U,       // MULve_8h8h
+    5622U,     // MULvvv_16B
+    1075844598U,       // MULvvv_2S
+    2150634998U,       // MULvvv_4H
+    3225425398U,       // MULvvv_4S
+    3226473974U,       // MULvvv_8B
+    1080038902U,       // MULvvv_8H
+    3726644418U,       // MVNIvi_lsl_2S
+    506467522U,        // MVNIvi_lsl_4H
+    3728741570U,       // MVNIvi_lsl_4S
+    509613250U,        // MVNIvi_lsl_8H
+    1579160770U,       // MVNIvi_msl_2S
+    1581257922U,       // MVNIvi_msl_4S
+    40904396U, // MVNww_asr
+    40904396U, // MVNww_lsl
+    40904396U, // MVNww_lsr
+    40904396U, // MVNww_ror
+    40904396U, // MVNxx_asr
+    40904396U, // MVNxx_lsl
+    40904396U, // MVNxx_lsr
+    40904396U, // MVNxx_ror
+    5088U,     // NEG16b
+    1074795488U,       // NEG2d
+    2149585888U,       // NEG2s
+    3224376288U,       // NEG4h
+    4199392U,  // NEG4s
+    1078989792U,       // NEG8b
+    2153780192U,       // NEG8h
+    3262129120U,       // NEGdd
+    6410U,     // NOT16b
+    1078991114U,       // NOT8b
+    5775U,     // ORNvvv_16B
+    3226474127U,       // ORNvvv_8B
+    40904335U, // ORNwww_asr
+    40904335U, // ORNwww_lsl
+    40904335U, // ORNwww_lsr
+    40904335U, // ORNwww_ror
+    40904335U, // ORNxxx_asr
+    40904335U, // ORNxxx_lsl
+    40904335U, // ORNxxx_lsr
+    40904335U, // ORNxxx_ror
+    270538747U,        // ORRvi_lsl_2S
+    1345329147U,       // ORRvi_lsl_4H
+    272635899U,        // ORRvi_lsl_4S
+    1348474875U,       // ORRvi_lsl_8H
+    6139U,     // ORRvvv_16B
+    3226474491U,       // ORRvvv_8B
+    40904699U, // ORRwwi
+    40904699U, // ORRwww_asr
+    40904699U, // ORRwww_lsl
+    40904699U, // ORRwww_lsr
+    40904699U, // ORRwww_ror
+    40904699U, // ORRxxi
+    40904699U, // ORRxxx_asr
+    40904699U, // ORRxxx_lsl
+    40904699U, // ORRxxx_lsr
+    40904699U, // ORRxxx_ror
+    656412886U,        // PMULL2vvv_1q2d
+    6295766U,  // PMULL2vvv_8h16b
+    689968567U,        // PMULLvvv_1q1d
+    3227522487U,       // PMULLvvv_8h8b
+    5634U,     // PMULvvv_16B
+    3226473986U,       // PMULvvv_8B
+    51631643U, // PRFM
+    51631643U, // PRFM_Wm_RegOffset
+    51631643U, // PRFM_Xm_RegOffset
+    309581339U,        // PRFM_lit
+    51631673U, // PRFUM
+    1140855152U,       // QRSHRUNvvi_16B
+    2149586618U,       // QRSHRUNvvi_2S
+    3224377018U,       // QRSHRUNvvi_4H
+    2218791280U,       // QRSHRUNvvi_4S
+    1078990522U,       // QRSHRUNvvi_8B
+    3294630256U,       // QRSHRUNvvi_8H
+    1140855142U,       // QSHRUNvvi_16B
+    2149586609U,       // QSHRUNvvi_2S
+    3224377009U,       // QSHRUNvvi_4H
+    2218791270U,       // QSHRUNvvi_4S
+    1078990513U,       // QSHRUNvvi_8B
+    3294630246U,       // QSHRUNvvi_8H
+    1140855065U,       // RADDHN2vvv_16b8h
+    2218791193U,       // RADDHN2vvv_4s2d
+    3294630169U,       // RADDHN2vvv_8h4s
+    2149586504U,       // RADDHNvvv_2s2d
+    3224376904U,       // RADDHNvvv_4h4s
+    1078990408U,       // RADDHNvvv_8b8h
+    6381U,     // RBIT16b
+    1078991085U,       // RBIT8b
+    3262130413U,       // RBITww
+    3262130413U,       // RBITxx
+    0U,        // RET
+    8399066U,  // RETx
+    4583U,     // REV16_16b
+    1078989287U,       // REV16_8b
+    3262128615U,       // REV16ww
+    3262128615U,       // REV16xx
+    4172U,     // REV32_16b
+    3224375372U,       // REV32_4h
+    1078988876U,       // REV32_8b
+    2153779276U,       // REV32_8h
+    3262128204U,       // REV32xx
+    4566U,     // REV64_16b
+    2149585366U,       // REV64_2s
+    3224375766U,       // REV64_4h
+    4198870U,  // REV64_4s
+    1078989270U,       // REV64_8b
+    2153779670U,       // REV64_8h
+    3262130526U,       // REVww
+    3262130526U,       // REVxx
+    40904694U, // RORVwww
+    40904694U, // RORVxxx
+    1140855094U,       // RSHRNvvi_16B
+    2149586559U,       // RSHRNvvi_2S
+    3224376959U,       // RSHRNvvi_4H
+    2218791222U,       // RSHRNvvi_4S
+    1078990463U,       // RSHRNvvi_8B
+    3294630198U,       // RSHRNvvi_8H
+    1140855056U,       // RSUBHN2vvv_16b8h
+    2218791184U,       // RSUBHN2vvv_4s2d
+    3294630160U,       // RSUBHN2vvv_8h4s
+    2149586496U,       // RSUBHNvvv_2s2d
+    3224376896U,       // RSUBHNvvv_4h4s
+    1078990400U,       // RSUBHNvvv_8b8h
+    3289387106U,       // SABAL2vvv_2d2s
+    1145049186U,       // SABAL2vvv_4s4h
+    73404514U, // SABAL2vvv_8h8b
+    1141904614U,       // SABALvvv_2d2s
+    2218792166U,       // SABALvvv_4s4h
+    3294631142U,       // SABALvvv_8h8b
+    67113454U, // SABAvvv_16B
+    1142952430U,       // SABAvvv_2S
+    2217742830U,       // SABAvvv_4H
+    3292533230U,       // SABAvvv_4S
+    3293581806U,       // SABAvvv_8B
+    1147146734U,       // SABAvvv_8H
+    3222278300U,       // SABDL2vvv_2d2s
+    1077940380U,       // SABDL2vvv_4s4h
+    6295708U,  // SABDL2vvv_8h8b
+    1074795822U,       // SABDLvvv_2d2s
+    2151683374U,       // SABDLvvv_4s4h
+    3227522350U,       // SABDLvvv_8h8b
+    4902U,     // SABDvvv_16B
+    1075843878U,       // SABDvvv_2S
+    2150634278U,       // SABDvvv_4H
+    3225424678U,       // SABDvvv_4S
+    3226473254U,       // SABDvvv_8B
+    1080038182U,       // SABDvvv_8H
+    73406194U, // SADALP16b8h
+    2234521330U,       // SADALP2s1d
+    3290437362U,       // SADALP4h2s
+    68163314U, // SADALP4s2d
+    1144002290U,       // SADALP8b4h
+    2218792690U,       // SADALP8h4s
+    3222278316U,       // SADDL2vvv_2d4s
+    1077940396U,       // SADDL2vvv_4s8h
+    6295724U,  // SADDL2vvv_8h16b
+    6297346U,  // SADDLP16b8h
+    2167412482U,       // SADDLP2s1d
+    3223328514U,       // SADDLP4h2s
+    1054466U,  // SADDLP4s2d
+    1076893442U,       // SADDLP8b4h
+    2151683842U,       // SADDLP8h4s
+    7350645U,  // SADDLV_1d4s
+    7350645U,  // SADDLV_1h16b
+    1081092469U,       // SADDLV_1h8b
+    3228576117U,       // SADDLV_1s4h
+    2154834293U,       // SADDLV_1s8h
+    1074795852U,       // SADDLvvv_2d2s
+    2151683404U,       // SADDLvvv_4s4h
+    3227522380U,       // SADDLvvv_8h8b
+    2148536757U,       // SADDW2vvv_2d4s
+    3225424309U,       // SADDW2vvv_4s8h
+    1080037813U,       // SADDW2vvv_8h16b
+    2148538873U,       // SADDWvvv_2d2s
+    3225426425U,       // SADDWvvv_4s4h
+    1080039929U,       // SADDWvvv_8h8b
+    40904807U, // SBCSwww
+    40904807U, // SBCSxxx
+    40903409U, // SBCwww
+    40903409U, // SBCxxx
+    40905351U, // SBFIZwwii
+    40905351U, // SBFIZxxii
+    40904207U, // SBFMwwii
+    40904207U, // SBFMxxii
+    40905306U, // SBFXwwii
+    40905306U, // SBFXxxii
+    1074795473U,       // SCVTF_2d
+    2149585873U,       // SCVTF_2s
+    4199377U,  // SCVTF_4s
+    40903633U, // SCVTF_Nddi
+    40903633U, // SCVTF_Nssi
+    3262129105U,       // SCVTFdd
+    3262129105U,       // SCVTFdw
+    40903633U, // SCVTFdwi
+    3262129105U,       // SCVTFdx
+    40903633U, // SCVTFdxi
+    3262129105U,       // SCVTFss
+    3262129105U,       // SCVTFsw
+    40903633U, // SCVTFswi
+    3262129105U,       // SCVTFsx
+    40903633U, // SCVTFsxi
+    40905065U, // SDIVwww
+    40905065U, // SDIVxxx
+    242229994U,        // SHA1C
+    3262129139U,       // SHA1H
+    242230792U,        // SHA1M
+    242231007U,        // SHA1P
+    3292532737U,       // SHA1SU0
+    71307320U, // SHA1SU1
+    242230274U,        // SHA256H
+    242229336U,        // SHA256H2
+    71307274U, // SHA256SU0
+    3292532801U,       // SHA256SU1
+    4936U,     // SHADDvvv_16B
+    1075843912U,       // SHADDvvv_2S
+    2150634312U,       // SHADDvvv_4H
+    3225424712U,       // SHADDvvv_4S
+    3226473288U,       // SHADDvvv_8B
+    1080038216U,       // SHADDvvv_8H
+    6295741U,  // SHLL16b8h
+    1074795937U,       // SHLL2s2d
+    2151683489U,       // SHLL4h4s
+    3222278333U,       // SHLL4s2d
+    3227522465U,       // SHLL8b8h
+    1077940413U,       // SHLL8h4s
+    40904035U, // SHLddi
+    5475U,     // SHLvvi_16B
+    2148537699U,       // SHLvvi_2D
+    1075844451U,       // SHLvvi_2S
+    2150634851U,       // SHLvvi_4H
+    3225425251U,       // SHLvvi_4S
+    3226473827U,       // SHLvvi_8B
+    1080038755U,       // SHLvvi_8H
+    1140855076U,       // SHRNvvi_16B
+    2149586543U,       // SHRNvvi_2S
+    3224376943U,       // SHRNvvi_4H
+    2218791204U,       // SHRNvvi_4S
+    1078990447U,       // SHRNvvi_8B
+    3294630180U,       // SHRNvvi_8H
+    4799U,     // SHSUBvvv_16B
+    1075843775U,       // SHSUBvvv_2S
+    2150634175U,       // SHSUBvvv_4H
+    3225424575U,       // SHSUBvvv_4S
+    3226473151U,       // SHSUBvvv_8B
+    1080038079U,       // SHSUBvvv_8H
+    242230461U,        // SLI
+    67114173U, // SLIvvi_16B
+    2215646397U,       // SLIvvi_2D
+    1142953149U,       // SLIvvi_2S
+    2217743549U,       // SLIvvi_4H
+    3292533949U,       // SLIvvi_4S
+    3293582525U,       // SLIvvi_8B
+    1147147453U,       // SLIvvi_8H
+    40903996U, // SMADDLxwwx
+    6008U,     // SMAXPvvv_16B
+    1075844984U,       // SMAXPvvv_2S
+    2150635384U,       // SMAXPvvv_4H
+    3225425784U,       // SMAXPvvv_4S
+    3226474360U,       // SMAXPvvv_8B
+    1080039288U,       // SMAXPvvv_8H
+    7350732U,  // SMAXV_1b16b
+    1081092556U,       // SMAXV_1b8b
+    3228576204U,       // SMAXV_1h4h
+    2154834380U,       // SMAXV_1h8h
+    7350732U,  // SMAXV_1s4s
+    6713U,     // SMAXvvv_16B
+    1075845689U,       // SMAXvvv_2S
+    2150636089U,       // SMAXvvv_4H
+    3225426489U,       // SMAXvvv_4S
+    3226475065U,       // SMAXvvv_8B
+    1080039993U,       // SMAXvvv_8H
+    8397578U,  // SMCi
+    5950U,     // SMINPvvv_16B
+    1075844926U,       // SMINPvvv_2S
+    2150635326U,       // SMINPvvv_4H
+    3225425726U,       // SMINPvvv_4S
+    3226474302U,       // SMINPvvv_8B
+    1080039230U,       // SMINPvvv_8H
+    7350686U,  // SMINV_1b16b
+    1081092510U,       // SMINV_1b8b
+    3228576158U,       // SMINV_1h4h
+    2154834334U,       // SMINV_1h8h
+    7350686U,  // SMINV_1s4s
+    5718U,     // SMINvvv_16B
+    1075844694U,       // SMINvvv_2S
+    2150635094U,       // SMINvvv_4H
+    3225425494U,       // SMINvvv_4S
+    3226474070U,       // SMINvvv_8B
+    1080038998U,       // SMINvvv_8H
+    3289387132U,       // SMLAL2vvv_2d4s
+    1145049212U,       // SMLAL2vvv_4s8h
+    73404540U, // SMLAL2vvv_8h16b
+    1141904637U,       // SMLALvve_2d2s
+    3289387132U,       // SMLALvve_2d4s
+    2218792189U,       // SMLALvve_4s4h
+    1145049212U,       // SMLALvve_4s8h
+    1141904637U,       // SMLALvvv_2d2s
+    2218792189U,       // SMLALvvv_4s4h
+    3294631165U,       // SMLALvvv_8h8b
+    3289387256U,       // SMLSL2vvv_2d4s
+    1145049336U,       // SMLSL2vvv_4s8h
+    73404664U, // SMLSL2vvv_8h16b
+    1141904858U,       // SMLSLvve_2d2s
+    3289387256U,       // SMLSLvve_2d4s
+    2218792410U,       // SMLSLvve_4s4h
+    1145049336U,       // SMLSLvve_4s8h
+    1141904858U,       // SMLSLvvv_2d2s
+    2218792410U,       // SMLSLvvv_4s4h
+    3294631386U,       // SMLSLvvv_8h8b
+    2154834361U,       // SMOVwb
+    1081092537U,       // SMOVwh
+    2154834361U,       // SMOVxb
+    1081092537U,       // SMOVxh
+    7350713U,  // SMOVxs
+    40903952U, // SMSUBLxwwx
+    40903719U, // SMULHxxx
+    3222278366U,       // SMULL2vvv_2d4s
+    1077940446U,       // SMULL2vvv_4s8h
+    6295774U,  // SMULL2vvv_8h16b
+    1074795966U,       // SMULLve_2d2s
+    3222278366U,       // SMULLve_2d4s
+    2151683518U,       // SMULLve_4s4h
+    1077940446U,       // SMULLve_4s8h
+    1074795966U,       // SMULLvvv_2d2s
+    2151683518U,       // SMULLvvv_4s4h
+    3227522494U,       // SMULLvvv_8h8b
+    6234U,     // SQABS16b
+    1074796634U,       // SQABS2d
+    2149587034U,       // SQABS2s
+    3224377434U,       // SQABS4h
+    4200538U,  // SQABS4s
+    1078990938U,       // SQABS8b
+    2153781338U,       // SQABS8h
+    3262130266U,       // SQABSbb
+    3262130266U,       // SQABSdd
+    3262130266U,       // SQABShh
+    3262130266U,       // SQABSss
+    40903526U, // SQADDbbb
+    40903526U, // SQADDddd
+    40903526U, // SQADDhhh
+    40903526U, // SQADDsss
+    4966U,     // SQADDvvv_16B
+    2148537190U,       // SQADDvvv_2D
+    1075843942U,       // SQADDvvv_2S
+    2150634342U,       // SQADDvvv_4H
+    3225424742U,       // SQADDvvv_4S
+    3226473318U,       // SQADDvvv_8B
+    1080038246U,       // SQADDvvv_8H
+    3289387122U,       // SQDMLAL2vvv_2d4s
+    1145049202U,       // SQDMLAL2vvv_4s8h
+    242230516U,        // SQDMLALdss
+    242230516U,        // SQDMLALdsv_2S
+    242230516U,        // SQDMLALdsv_4S
+    242230516U,        // SQDMLALshh
+    242230516U,        // SQDMLALshv_4H
+    242230516U,        // SQDMLALshv_8H
+    1141904628U,       // SQDMLALvve_2d2s
+    3289387122U,       // SQDMLALvve_2d4s
+    2218792180U,       // SQDMLALvve_4s4h
+    1145049202U,       // SQDMLALvve_4s8h
+    1141904628U,       // SQDMLALvvv_2d2s
+    2218792180U,       // SQDMLALvvv_4s4h
+    3289387246U,       // SQDMLSL2vvv_2d4s
+    1145049326U,       // SQDMLSL2vvv_4s8h
+    242230737U,        // SQDMLSLdss
+    242230737U,        // SQDMLSLdsv_2S
+    242230737U,        // SQDMLSLdsv_4S
+    242230737U,        // SQDMLSLshh
+    242230737U,        // SQDMLSLshv_4H
+    242230737U,        // SQDMLSLshv_8H
+    1141904849U,       // SQDMLSLvve_2d2s
+    3289387246U,       // SQDMLSLvve_2d4s
+    2218792401U,       // SQDMLSLvve_4s4h
+    1145049326U,       // SQDMLSLvve_4s8h
+    1141904849U,       // SQDMLSLvvv_2d2s
+    2218792401U,       // SQDMLSLvvv_4s4h
+    40903700U, // SQDMULHhhh
+    40903700U, // SQDMULHhhv_4H
+    40903700U, // SQDMULHhhv_8H
+    40903700U, // SQDMULHsss
+    40903700U, // SQDMULHssv_2S
+    40903700U, // SQDMULHssv_4S
+    1075844116U,       // SQDMULHve_2s4s
+    2150634516U,       // SQDMULHve_4h8h
+    3225424916U,       // SQDMULHve_4s4s
+    1080038420U,       // SQDMULHve_8h8h
+    1075844116U,       // SQDMULHvvv_2S
+    2150634516U,       // SQDMULHvvv_4H
+    3225424916U,       // SQDMULHvvv_4S
+    1080038420U,       // SQDMULHvvv_8H
+    3222278348U,       // SQDMULL2vvv_2d4s
+    1077940428U,       // SQDMULL2vvv_4s8h
+    40904110U, // SQDMULLdss
+    40904110U, // SQDMULLdsv_2S
+    40904110U, // SQDMULLdsv_4S
+    40904110U, // SQDMULLshh
+    40904110U, // SQDMULLshv_4H
+    40904110U, // SQDMULLshv_8H
+    1074795950U,       // SQDMULLve_2d2s
+    3222278348U,       // SQDMULLve_2d4s
+    2151683502U,       // SQDMULLve_4s4h
+    1077940428U,       // SQDMULLve_4s8h
+    1074795950U,       // SQDMULLvvv_2d2s
+    2151683502U,       // SQDMULLvvv_4s4h
+    5093U,     // SQNEG16b
+    1074795493U,       // SQNEG2d
+    2149585893U,       // SQNEG2s
+    3224376293U,       // SQNEG4h
+    4199397U,  // SQNEG4s
+    1078989797U,       // SQNEG8b
+    2153780197U,       // SQNEG8h
+    3262129125U,       // SQNEGbb
+    3262129125U,       // SQNEGdd
+    3262129125U,       // SQNEGhh
+    3262129125U,       // SQNEGss
+    40903709U, // SQRDMULHhhh
+    40903709U, // SQRDMULHhhv_4H
+    40903709U, // SQRDMULHhhv_8H
+    40903709U, // SQRDMULHsss
+    40903709U, // SQRDMULHssv_2S
+    40903709U, // SQRDMULHssv_4S
+    1075844125U,       // SQRDMULHve_2s4s
+    2150634525U,       // SQRDMULHve_4h8h
+    3225424925U,       // SQRDMULHve_4s4s
+    1080038429U,       // SQRDMULHve_8h8h
+    1075844125U,       // SQRDMULHvvv_2S
+    2150634525U,       // SQRDMULHvvv_4H
+    3225424925U,       // SQRDMULHvvv_4S
+    1080038429U,       // SQRDMULHvvv_8H
+    40904047U, // SQRSHLbbb
+    40904047U, // SQRSHLddd
+    40904047U, // SQRSHLhhh
+    40904047U, // SQRSHLsss
+    5487U,     // SQRSHLvvv_16B
+    2148537711U,       // SQRSHLvvv_2D
+    1075844463U,       // SQRSHLvvv_2S
+    2150634863U,       // SQRSHLvvv_4H
+    3225425263U,       // SQRSHLvvv_4S
+    3226473839U,       // SQRSHLvvv_8B
+    1080038767U,       // SQRSHLvvv_8H
+    40904317U, // SQRSHRNbhi
+    40904317U, // SQRSHRNhsi
+    40904317U, // SQRSHRNsdi
+    1140855092U,       // SQRSHRNvvi_16B
+    2149586557U,       // SQRSHRNvvi_2S
+    3224376957U,       // SQRSHRNvvi_4H
+    2218791220U,       // SQRSHRNvvi_4S
+    1078990461U,       // SQRSHRNvvi_8B
+    3294630196U,       // SQRSHRNvvi_8H
+    40904378U, // SQRSHRUNbhi
+    40904378U, // SQRSHRUNhsi
+    40904378U, // SQRSHRUNsdi
+    40905008U, // SQSHLUbbi
+    40905008U, // SQSHLUddi
+    40905008U, // SQSHLUhhi
+    40905008U, // SQSHLUssi
+    6448U,     // SQSHLUvvi_16B
+    2148538672U,       // SQSHLUvvi_2D
+    1075845424U,       // SQSHLUvvi_2S
+    2150635824U,       // SQSHLUvvi_4H
+    3225426224U,       // SQSHLUvvi_4S
+    3226474800U,       // SQSHLUvvi_8B
+    1080039728U,       // SQSHLUvvi_8H
+    40904033U, // SQSHLbbb
+    40904033U, // SQSHLbbi
+    40904033U, // SQSHLddd
+    40904033U, // SQSHLddi
+    40904033U, // SQSHLhhh
+    40904033U, // SQSHLhhi
+    40904033U, // SQSHLssi
+    40904033U, // SQSHLsss
+    5473U,     // SQSHLvvi_16B
+    2148537697U,       // SQSHLvvi_2D
+    1075844449U,       // SQSHLvvi_2S
+    2150634849U,       // SQSHLvvi_4H
+    3225425249U,       // SQSHLvvi_4S
+    3226473825U,       // SQSHLvvi_8B
+    1080038753U,       // SQSHLvvi_8H
+    5473U,     // SQSHLvvv_16B
+    2148537697U,       // SQSHLvvv_2D
+    1075844449U,       // SQSHLvvv_2S
+    2150634849U,       // SQSHLvvv_4H
+    3225425249U,       // SQSHLvvv_4S
+    3226473825U,       // SQSHLvvv_8B
+    1080038753U,       // SQSHLvvv_8H
+    40904301U, // SQSHRNbhi
+    40904301U, // SQSHRNhsi
+    40904301U, // SQSHRNsdi
+    1140855074U,       // SQSHRNvvi_16B
+    2149586541U,       // SQSHRNvvi_2S
+    3224376941U,       // SQSHRNvvi_4H
+    2218791202U,       // SQSHRNvvi_4S
+    1078990445U,       // SQSHRNvvi_8B
+    3294630178U,       // SQSHRNvvi_8H
+    40904369U, // SQSHRUNbhi
+    40904369U, // SQSHRUNhsi
+    40904369U, // SQSHRUNsdi
+    40903388U, // SQSUBbbb
+    40903388U, // SQSUBddd
+    40903388U, // SQSUBhhh
+    40903388U, // SQSUBsss
+    4828U,     // SQSUBvvv_16B
+    2148537052U,       // SQSUBvvv_2D
+    1075843804U,       // SQSUBvvv_2S
+    2150634204U,       // SQSUBvvv_4H
+    3225424604U,       // SQSUBvvv_4S
+    3226473180U,       // SQSUBvvv_8B
+    1080038108U,       // SQSUBvvv_8H
+    1075844771U,       // SQXTN2d2s
+    1145049430U,       // SQXTN2d4s
+    3151523U,  // SQXTN4s4h
+    73404758U, // SQXTN4s8h
+    2214596950U,       // SQXTN8h16b
+    2152732323U,       // SQXTN8h8b
+    3262129827U,       // SQXTNbh
+    3262129827U,       // SQXTNhs
+    3262129827U,       // SQXTNsd
+    1075844804U,       // SQXTUN2d2s
+    1145049467U,       // SQXTUN2d4s
+    3151556U,  // SQXTUN4s4h
+    73404795U, // SQXTUN4s8h
+    2214596987U,       // SQXTUN8h16b
+    2152732356U,       // SQXTUN8h8b
+    3262129860U,       // SQXTUNbh
+    3262129860U,       // SQXTUNhs
+    3262129860U,       // SQXTUNsd
+    4920U,     // SRHADDvvv_16B
+    1075843896U,       // SRHADDvvv_2S
+    2150634296U,       // SRHADDvvv_4H
+    3225424696U,       // SRHADDvvv_4S
+    3226473272U,       // SRHADDvvv_8B
+    1080038200U,       // SRHADDvvv_8H
+    242230472U,        // SRI
+    67114184U, // SRIvvi_16B
+    2215646408U,       // SRIvvi_2D
+    1142953160U,       // SRIvvi_2S
+    2217743560U,       // SRIvvi_4H
+    3292533960U,       // SRIvvi_4S
+    3293582536U,       // SRIvvi_8B
+    1147147464U,       // SRIvvi_8H
+    40904063U, // SRSHLddd
+    5503U,     // SRSHLvvv_16B
+    2148537727U,       // SRSHLvvv_2D
+    1075844479U,       // SRSHLvvv_2S
+    2150634879U,       // SRSHLvvv_4H
+    3225425279U,       // SRSHLvvv_4S
+    3226473855U,       // SRSHLvvv_8B
+    1080038783U,       // SRSHLvvv_8H
+    40904652U, // SRSHRddi
+    6092U,     // SRSHRvvi_16B
+    2148538316U,       // SRSHRvvi_2D
+    1075845068U,       // SRSHRvvi_2S
+    2150635468U,       // SRSHRvvi_4H
+    3225425868U,       // SRSHRvvi_4S
+    3226474444U,       // SRSHRvvi_8B
+    1080039372U,       // SRSHRvvi_8H
+    242229760U,        // SRSRA
+    67113472U, // SRSRAvvi_16B
+    2215645696U,       // SRSRAvvi_2D
+    1142952448U,       // SRSRAvvi_2S
+    2217742848U,       // SRSRAvvi_4H
+    3292533248U,       // SRSRAvvi_4S
+    3293581824U,       // SRSRAvvi_8B
+    1147146752U,       // SRSRAvvi_8H
+    6295740U,  // SSHLLvvi_16B
+    1074795936U,       // SSHLLvvi_2S
+    2151683488U,       // SSHLLvvi_4H
+    3222278332U,       // SSHLLvvi_4S
+    3227522464U,       // SSHLLvvi_8B
+    1077940412U,       // SSHLLvvi_8H
+    40904077U, // SSHLddd
+    5517U,     // SSHLvvv_16B
+    2148537741U,       // SSHLvvv_2D
+    1075844493U,       // SSHLvvv_2S
+    2150634893U,       // SSHLvvv_4H
+    3225425293U,       // SSHLvvv_4S
+    3226473869U,       // SSHLvvv_8B
+    1080038797U,       // SSHLvvv_8H
+    40904666U, // SSHRddi
+    6106U,     // SSHRvvi_16B
+    2148538330U,       // SSHRvvi_2D
+    1075845082U,       // SSHRvvi_2S
+    2150635482U,       // SSHRvvi_4H
+    3225425882U,       // SSHRvvi_4S
+    3226474458U,       // SSHRvvi_8B
+    1080039386U,       // SSHRvvi_8H
+    242229774U,        // SSRA
+    67113486U, // SSRAvvi_16B
+    2215645710U,       // SSRAvvi_2D
+    1142952462U,       // SSRAvvi_2S
+    2217742862U,       // SSRAvvi_4H
+    329253